Data processing device and data processing method

ABSTRACT

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rater is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 14/905,213, filedJan. 14, 2016, which is a U.S. National Stage Application ofInternational Application No. PCT/JP2015/063250, filed May 8, 2015,which is based on and claims priority to Japanese Application No.2014-104806, filed May 21, 2014, the entire contents of each of whichare incorporated herein by reference.

TECHNICAL FIELD

The present technology relates to a data processing device and a dataprocessing method, and more particularly, a data processing device and adata processing method, which are capable of securing excellentcommunication quality in data transmission using an LDPC code, forexample.

BACKGROUND ART

Some of the information disclosed in this specification and the drawingswas provided by Samsung Electronics Co., Ltd. (hereinafter referred toas Samsung), LG Electronics Inc., NERC, and CRC/ETRI (indicated in thedrawings).

A low density parity check (LDPC) code has a high error correctioncapability, and in recent years, the LDPC code has widely been employedin transmission schemes of digital broadcasting such as Digital VideoBroadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe and the like, orAdvanced Television Systems Committee (ATSC) 3.0 of the USA and the like(for example, see Non-Patent Literature 1).

From a recent study, it is known that performance near a Shannon limitis obtained from the LDPC code when a code length increases, similar toa turbo code. Because the LDPC code has a property that a shortestdistance is proportional to the code length, the LDPC code hasadvantages of a block error probability characteristic being superiorand a so-called error floor phenomenon observed in a decodingcharacteristic of the turbo code being rarely generated, ascharacteristics thereof.

CITATION LIST Non-Patent Literature

-   Non-Patent Literature 1: DVB-S.2: ETSI EN 302 307 V1.2.1 (2009-08)

SUMMARY OF INVENTION Technical Problem

In data transmission using the LDPC code, for example, the LDPC code isconverted into a symbol of an orthogonal modulation (digital modulation)such as Quadrature Phase Shift Keying (QPSK), and the symbol is mappedto a signal point of the orthogonal modulation and transmitted.

The data transmission using the LDPC code has spread worldwide, andthere is a demand to secure excellent communication (transmission)quality.

The present technology was made in light of the foregoing, and it isdesirable to secure excellent communication quality in data transmissionusing the LDPC code.

Solution to Problem

A first data processing device/method according to the presenttechnology is a data processing device/method including: an encodingunit/step configured to perform LDPC encoding based on a parity checkmatrix of an LDPC code in which a code length N is 16200 bits and anencoding rate r is 10/15; a group-wise interleaving unit/step configuredto perform group-wise interleave of interleaving the LDPC code in unitsof bit groups of 360 bits; and a mapping unit/step configured to map theLDPC code to any of 16 signal points decided in a modulation scheme inunits of 4 bits, wherein in the group-wise interleave. An (i+1)-th bitgroup from a head of the LDPC code is indicated by a bit group i, asequence of bit groups 0 to 44 of the LDPC code of 16200 bits isinterleaved into a sequence of bit groups 27, 11, 20, 1, 7, 5, 29, 35,9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4,31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.The LDPC code includes an information bit and a parity bit, the paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

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In the first data processing device/method, LDPC encoding is performedbased on a parity check matrix of an LDPC code in which a code length Nis 16200 bits and an encoding rate r is 10/15, group-wise interleave ofinterleaving the LDPC code is performed in units of bit groups of 360bits, and the LDPC code is mapped to any of 16 signal points decided ina modulation scheme in units of 4 bits. In the group-wise interleave,when an (i+1)-th bit group from a head of the LDPC code is indicated bya bit group i, a sequence of bit groups 0 to 44 of the LDPC code of16200 bits is interleaved into a sequence of bit groups

27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23,16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39,43, 21, 3, 22, 26, 33, and 38.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

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A second data processing device/method according to the presenttechnology is a data processing device/method including: a group-wisedeinterleaving unit/step configured to restore a sequence of an LDPCcode that has undergone group-wise interleave and has been obtained fromdata transmitted from a transmitting device to an original sequence, thetransmitting device including an encoding unit configured to performLDPC encoding based on a parity check matrix of the LDPC code in which acode length N is 16200 bits and an encoding rate r is 10/15, agroup-wise interleaving unit configured to perform the group-wiseinterleave of interleaving the LDPC code in units of bit groups of 360bits, and a mapping unit configured to map the LDPC code to any of 16signal points decided in a modulation scheme in units of 4 bits. In thegroup-wise interleave, when an (i+1)-th bit group from a head of theLDPC code is indicated by a bit group i, a sequence of bit groups 0 to44 of the LDPC code of 16200 bits is interleaved into a sequence of bitgroups

27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23,16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39,43, 21, 3, 22, 26, 33, and 38.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 38214384 4470 4884 5012 5036 5084 5101 5271 5281 5353 505 915 1156 1269 15181650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 44394532 4940 5011 5076 5113 5367 268 346 650 919 1260 4389 4653 4721 48385054 5157 5162 5275 5362 220 236 828 1590 1792 3259 3647 4276 4281 43254963 4974 5003 5037 381 737 1099 1409 2364 2955 3228 3341 3473 3985 42574730 5173 5242 88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 45014901 5047 749 1502 2201 3189 2873 3245 3427 2158 2605 3165 1 3438 360610 3019 5221 371 2901 2923 9 3935 4683 1937 3502 3735 507 3128 4994 253854 4550 1178 4737 5366 2 223 5304 1146 5175 5197 1816 2313 3649 7401951 3844 1320 3703 4791 1754 2905 4058 7 917 5277 3048 3954 5396 48044824 5105 2812 3895 5226 0 5318 5358 1483 2324 4826 2266 4752 5387.

In the second data processing device, a sequence of an LDPC code thathas undergone group-wise interleave and has been obtained from datatransmitted from a transmitting device is restored to an originalsequence, the transmitting device including an encoding unit configuredto perform LDPC encoding based on a parity check matrix of the LDPC codein which a code length N is 16200 bits and an encoding rate r is 10/15,a group-wise interleaving unit configured to perform the group-wiseinterleave of interleaving the LDPC code in units of bit groups of 360bits, and a mapping unit configured to map the LDPC code to any of 16signal points decided in a modulation scheme in units of 4 bits. In thegroup-wise interleave, when an (i+1)-th bit group from a head of theLDPC code is indicated by a bit group i, a sequence of bit groups 0 to44 of the LDPC code of 16200 bits is interleaved into a sequence of bitgroups

27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23,16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39,43, 21, 3, 22, 26, 33, and 38.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 38214384 4470 4884 5012 5036 5084 5101 5271 5281 5353 505 915 1156 1269 15181650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 44394532 4940 5011 5076 5113 5367 268 346 650 919 1260 4389 4653 4721 48385054 5157 5162 5275 5362 220 236 828 1590 1792 3259 3647 4276 4281 43254963 4974 5003 5037 381 737 1099 1409 2364 2955 3228 3341 3473 3985 42574730 5173 5242 88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 45014901 5047 749 1502 2201 3189 2873 3245 3427 2158 2605 3165 1 3438 360610 3019 5221 371 2901 2923 9 3935 4683 1937 3502 3735 507 3128 4994 253854 4550 1178 4737 5366 2 223 5304 1146 5175 5197 1816 2313 3649 7401951 3844 1320 3703 4791 1754 2905 4058 7 917 5277 3048 3954 5396 48044824 5105 2812 3895 5226 0 5318 5358 1483 2324 4826 2266 4752 5387.

A third data processing device/method according to the presenttechnology is a data processing device/method including: an encodingunit/step configured to perform LDPC encoding based on a parity checkmatrix of an LDPC code in which a code length N is 16200 bits and anencoding rate r is 12/15; a group-wise interleaving unit/step configuredto perform group-wise interleave of interleaving the LDPC code in unitsof bit groups of 360 bits; and a mapping unit/step configured to map theLDPC code to any of 16 signal points decided in a modulation scheme inunits of 4 bits. In the group-wise interleave, when an (i+1)-th bitgroup from a head of the LDPC code is indicated by a bit group i, asequence of bit groups 0 to 44 of the LDPC code of 16200 bits isinterleaved into a sequence of bit groups

3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16,9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43,35, 36, 13, 39, 12, 1, and 31.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155 59 136528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847 155 245 311 6211114 1269 1281 1783 1995 2047 2672 2803 2885 3014 79 870 974 1326 14491531 2077 2317 2467 2627 2811 3083 3101 3132 4 582 660 902 1048 14821697 1744 1928 2628 2699 2728 3045 3104 175 395 429 1027 1061 1068 11541168 1175 2147 2359 2376 2613 2682 1388 2241 3118 3148 143 506 2067 31481594 2217 2705 398 988 2551 1149 2588 2654 678 2844 3115 1508 1547 19541199 1267 1710 2589 3163 3207 1 2583 2974 2766 2897 3166 929 1823 27421113 3007 3239 1753 2478 3127 0 509 1811 1672 2646 2984 965 1462 3230 31077 2917 1183 1316 1662 968 1593 3239 64 1996 2226 1442 2058 3181 513973 1058 1263 3185 3229 681 1394 3017 419 2853 3217 3 2404 3175 24172792 2854 1879 2940 3235 647 1704 3060.

In the third data processing device/method, LDPC encoding is performedbased on a parity check matrix of an LDPC code in which a code length Nis 16200 bits and an encoding rate r is 12/15, group-wise interleave ofinterleaving the LDPC code is performed in units of bit groups of 360bits, and the LDPC code is mapped to any of 16 signal points decided ina modulation scheme in units of 4 bits. In the group-wise interleave,when an (i+1)-th bit group from a head of the LDPC code is indicated bya bit group i, a sequence of bit groups 0 to 44 of the LDPC code of16200 bits is interleaved into a sequence of bit groups

3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16,9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43,35, 36, 13, 39, 12, 1, and 31.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155 59 136528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847 155 245 311 6211114 1269 1281 1783 1995 2047 2672 2803 2885 3014 79 870 974 1326 14491531 2077 2317 2467 2627 2811 3083 3101 3132 4 582 660 902 1048 14821697 1744 1928 2628 2699 2728 3045 3104 175 395 429 1027 1061 1068 11541168 1175 2147 2359 2376 2613 2682 1388 2241 3118 3148 143 506 2067 31481594 2217 2705 398 988 2551 1149 2588 2654 678 2844 3115 1508 1547 19541199 1267 1710 2589 3163 3207 1 2583 2974 2766 2897 3166 929 1823 27421113 3007 3239 1753 2478 3127 0 509 1811 1672 2646 2984 965 1462 3230 31077 2917 1183 1316 1662 968 1593 3239 64 1996 2226 1442 2058 3181 513973 1058 1263 3185 3229 681 1394 3017 419 2853 3217 3 2404 3175 24172792 2854 1879 2940 3235 647 1704 3060.

A fourth data processing device/method according to the presenttechnology is a data processing device/method including: a group-wisedeinterleaving unit/step configured to restore a sequence of an LDPCcode that has undergone group-wise interleave and has been obtained fromdata transmitted from a transmitting device to an original sequence, thetransmitting device including an encoding unit configured to performLDPC encoding based on a parity check matrix of the LDPC code in which acode length N is 16200 bits and an encoding rate r is 12/15, agroup-wise interleaving unit configured to perform the group-wiseinterleave of interleaving the LDPC code in units of bit groups of 360bits, and a mapping unit configured to map the LDPC code to any of 16signal points decided in a modulation scheme in units of 4 bits. In thegroup-wise interleave, when an (i+1)-th bit group from a head of theLDPC code is indicated by a bit group i, a sequence of bit groups 0 to44 of the LDPC code of 16200 bits is interleaved into a sequence of bitgroups

3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16,9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43,35, 36, 13, 39, 12, 1, and 31.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155 59 136528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847 155 245 311 6211114 1269 1281 1783 1995 2047 2672 2803 2885 3014 79 870 974 1326 14491531 2077 2317 2467 2627 2811 3083 3101 3132 4 582 660 902 1048 14821697 1744 1928 2628 2699 2728 3045 3104 175 395 429 1027 1061 1068 11541168 1175 2147 2359 2376 2613 2682 1388 2241 3118 3148 143 506 2067 31481594 2217 2705 398 988 2551 1149 2588 2654 678 2844 3115 1508 1547 19541199 1267 1710 2589 3163 3207 1 2583 2974 2766 2897 3166 929 1823 27421113 3007 3239 1753 2478 3127 0 509 1811 1672 2646 2984 965 1462 3230 31077 2917 1183 1316 1662 968 1593 3239 64 1996 2226 1442 2058 3181 513973 1058 1263 3185 3229 681 1394 3017 419 2853 3217 3 2404 3175 24172792 2854 1879 2940 3235 647 1704 3060.

In the fourth data processing device, a sequence of an LDPC code thathas undergone group-wise interleave and has been obtained from datatransmitted from a transmitting device is restored to an originalsequence, the transmitting device including an encoding unit configuredto perform LDPC encoding based on a parity check matrix of the LDPC codein which a code length N is 16200 bits and an encoding rate r is 12/15,a group-wise interleaving unit configured to perform the group-wiseinterleave of interleaving the LDPC code in units of bit groups of 360bits, and a mapping unit configured to map the LDPC code to any of 16signal points decided in a modulation scheme in units of 4 bits. In thegroup-wise interleave, when an (i+1)-th bit group from a head of theLDPC code is indicated by a bit group i, a sequence of bit groups 0 to44 of the LDPC code of 16200 bits is interleaved into a sequence of bitgroups

3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16,9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43,35, 36, 13, 39, 12, 1, and 31.

The LDPC code includes an information bit and a parity bit. The paritycheck matrix includes an information matrix portion corresponding to theinformation bit and a parity matrix portion corresponding to the paritybit. The information matrix portion is represented by a parity checkmatrix initial value table. The parity check matrix initial value tableis a table in which a position of a 1 element of the information matrixportion is indicated for every 360 columns, and includes

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155 59 136528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847 155 245 311 6211114 1269 1281 1783 1995 2047 2672 2803 2885 3014 79 870 974 1326 14491531 2077 2317 2467 2627 2811 3083 3101 3132 4 582 660 902 1048 14821697 1744 1928 2628 2699 2728 3045 3104 175 395 429 1027 1061 1068 11541168 1175 2147 2359 2376 2613 2682 1388 2241 3118 3148 143 506 2067 31481594 2217 2705 398 988 2551 1149 2588 2654 678 2844 3115 1508 1547 19541199 1267 1710 2589 3163 3207 1 2583 2974 2766 2897 3166 929 1823 27421113 3007 3239 1753 2478 3127 0 509 1811 1672 2646 2984 965 1462 3230 31077 2917 1183 1316 1662 968 1593 3239 64 1996 2226 1442 2058 3181 513973 1058 1263 3185 3229 681 1394 3017 419 2853 3217 3 2404 3175 24172792 2854 1879 2940 3235 647 1704 3060.

The data processing device may be an independent device and may be aninternal block constituting one device.

Advantageous Effects of Invention

According to the present technology, it is possible to secure excellentcommunication quality in data transmission using the LDPC code.

The effects described herein are not necessarily limited and may includeany effect described in the present disclosure.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an illustration of a parity check matrix H of an LDPC code.

FIG. 2 is a flowchart illustrating a decoding sequence of an LDPC code.

FIG. 3 is an illustration of an example of a parity check matrix of anLDPC code.

FIG. 4 is an illustration of an example of a Tanner graph of a paritycheck matrix.

FIG. 5 is an illustration of an example of a variable node.

FIG. 6 is an illustration of an example of a check node.

FIG. 7 is an illustration of a configuration example of an embodiment ofa transmission system to which the present invention is applied.

FIG. 8 is a block diagram illustrating a configuration example of atransmitting device 11.

FIG. 9 is a block diagram illustrating a configuration example of a bitinterleaver 116.

FIG. 10 is an illustration of an example of a parity check matrix.

FIG. 11 is an illustration of an example of a parity matrix.

FIG. 12 is an illustration of the parity check matrix of the LDPC codethat is defined in the standard of the DVB-T.2.

FIG. 13 is an illustration of the parity check matrix of the LDPC codethat is defined in the standard of the DVB-T.2.

FIG. 14 is an illustration of an example of a Tanner graph for decodingof an LDPC code.

FIG. 15 is an illustration of an example of a parity matrix H_(T)becoming a staircase structure and a Tanner graph corresponding to theparity matrix H_(T).

FIG. 16 is an illustration of an example of a parity matrix H_(T) of aparity check matrix H corresponding to an LDPC code after parityinterleave.

FIG. 17 is a flowchart illustrating an example of a process performed bya bit interleaver 116 and a mapper 117.

FIG. 18 is a block diagram illustrating a configuration example of anLDPC encoder 115.

FIG. 19 is a flowchart illustrating processing of an example of an LDPCencoder 115.

FIG. 20 is an illustration of an example of a parity check matrixinitial value table in which an encoding rate is 1/4 and a code lengthis 16200.

FIG. 21 is an illustration of a method of calculating a parity checkmatrix H from a parity check matrix initial value table.

FIG. 22 is an illustration of a structure of a parity check matrix.

FIG. 23 is an illustration of an example of the parity check matrixinitial value table.

FIG. 24 is an illustration of an A matrix generated from a parity checkmatrix initial value table.

FIG. 25 is an illustration of parity interleave of a B matrix.

FIG. 26 is an illustration of a C matrix generated from a parity checkmatrix initial value table.

FIG. 27 is an illustration of parity interleave of a D matrix.

FIG. 28 is an illustration of a parity check matrix obtained byperforming a column permutation serving as parity deinterleave forrestoring parity interleave to an original state on a parity checkmatrix.

FIG. 29 is an illustration of a transformed parity check matrix obtainedby performing a row permutation on a parity check matrix.

FIG. 30 is an illustration of an example of the parity check matrixinitial value table.

FIG. 31 is an illustration of an example of the parity check matrixinitial value table.

FIG. 32 is an illustration of an example of the parity check matrixinitial value table.

FIG. 33 is an illustration of an example of the parity check matrixinitial value table.

FIG. 34 is an illustration of an example of the parity check matrixinitial value table.

FIG. 35 is an illustration of an example of the parity check matrixinitial value table.

FIG. 36 is an illustration of an example of the parity check matrixinitial value table.

FIG. 37 is an illustration of an example of the parity check matrixinitial value table.

FIG. 38 is an illustration of an example of the parity check matrixinitial value table.

FIG. 39 is an illustration of an example of the parity check matrixinitial value table.

FIG. 40 is an illustration of an example of the parity check matrixinitial value table.

FIG. 41 is an illustration of an example of the parity check matrixinitial value table.

FIG. 42 is an illustration of an example of the parity check matrixinitial value table.

FIG. 43 is an illustration of an example of the parity check matrixinitial value table.

FIG. 44 is an illustration of an example of the parity check matrixinitial value table.

FIG. 45 is an illustration of an example of the parity check matrixinitial value table.

FIG. 46 is an illustration of an example of the parity check matrixinitial value table.

FIG. 47 is an illustration of an example of the parity check matrixinitial value table.

FIG. 48 is an illustration of an example of the parity check matrixinitial value table.

FIG. 49 is an illustration of an example of the parity check matrixinitial value table.

FIG. 50 is an illustration of an example of the parity check matrixinitial value table.

FIG. 51 is an illustration of an example of the parity check matrixinitial value table.

FIG. 52 is an illustration of an example of the parity check matrixinitial value table.

FIG. 53 is an illustration of an example of the parity check matrixinitial value table.

FIG. 54 is an illustration of an example of the parity check matrixinitial value table.

FIG. 55 is an illustration of an example of the parity check matrixinitial value table.

FIG. 56 is an illustration of an example of the parity check matrixinitial value table.

FIG. 57 is an illustration of an example of the parity check matrixinitial value table.

FIG. 58 is an illustration of an example of the parity check matrixinitial value table.

FIG. 59 is an illustration of an example of the parity check matrixinitial value table.

FIG. 60 is an illustration of an example of the parity check matrixinitial value table.

FIG. 61 is an illustration of an example of the parity check matrixinitial value table.

FIG. 62 is an illustration of an example of the parity check matrixinitial value table.

FIG. 63 is an illustration of an example of the parity check matrixinitial value table.

FIG. 64 is an illustration of an example of the parity check matrixinitial value table.

FIG. 65 is an illustration of an example of the parity check matrixinitial value table.

FIG. 66 is an illustration of an example of the parity check matrixinitial value table.

FIG. 67 is an illustration of an example of the parity check matrixinitial value table.

FIG. 68 is an illustration of an example of the parity check matrixinitial value table.

FIG. 69 is an illustration of an example of the parity check matrixinitial value table.

FIG. 70 is an illustration of an example of the parity check matrixinitial value table.

FIG. 71 is an illustration of an example of the parity check matrixinitial value table.

FIG. 72 is an illustration of an example of the parity check matrixinitial value table.

FIG. 73 is an illustration of an example of a tanner graph of anensemble of a degree sequence in which a column weight is 3, and a rowweight is 6.

FIG. 74 is an illustration of an example of a tanner graph of anensemble of a multi-edge type.

FIG. 75 is an illustration of a parity check matrix.

FIG. 76 is an illustration of a parity check matrix.

FIG. 77 is an illustration of a parity check matrix.

FIG. 78 is an illustration of a parity check matrix.

FIG. 79 is an illustration of a parity check matrix.

FIG. 80 is an illustration of a parity check matrix.

FIG. 81 is an illustration of a parity check matrix.

FIG. 82 is an illustration of a parity check matrix.

FIG. 83 is an illustration of an example of a constellation when amodulation scheme is 16QAM.

FIG. 84 is an illustration of an example of a constellation when amodulation scheme is 64QAM.

FIG. 85 is an illustration of an example of a constellation when amodulation scheme is 256QAM.

FIG. 86 is an illustration of an example of a constellation when amodulation scheme is 1024QAM.

FIG. 87 is an illustration of an example of a constellation when amodulation scheme is 4096QAM.

FIG. 88 is an illustration of an example of a constellation when amodulation scheme is 4096QAM.

FIG. 89 is an illustration of an example of coordinates of a signalpoint of a UC when a modulation scheme is QPSK.

FIG. 90 is an illustration of an example of coordinates of a signalpoint of a 2D NUC when a modulation scheme is 16QAM.

FIG. 91 is an illustration of an example of coordinates of a signalpoint of a 2D NUC when a modulation scheme is 64QAM.

FIG. 92 is an illustration of an example of coordinates of a signalpoint of a 2D NUC when a modulation scheme is 256QAM.

FIG. 93 is an illustration of an example of coordinates of a signalpoint of a 2D NUC when a modulation scheme is 256QAM.

FIG. 94 is an illustration of an example of coordinates of a signalpoint of a 1D NUC when a modulation scheme is 1024QAM.

FIG. 95 is an illustration of relations of a symbol y of 1024QAM with areal part Re (z_(q)) and an imaginary part Im (z_(q)) of a complexnumber serving as coordinates of a signal point z_(q) of a 1D NUCcorresponding to the symbol y.

FIG. 96 is an illustration of an example of coordinates of a signalpoint of a 1D NUC when a modulation scheme is 4096QAM.

FIG. 97 is an illustration of relations of a symbol y of 4096QAM with areal part Re (z_(q)) and an imaginary part Im (z_(q)) of a complexnumber serving as coordinates of a signal point z_(q) of a 1D NUCcorresponding to the symbol y.

FIG. 98 is an illustration of another example of a constellation when amodulation scheme is 16QAM.

FIG. 99 is an illustration of another example of a constellation when amodulation scheme is 64QAM.

FIG. 100 is an illustration of another example of a constellation when amodulation scheme is 256QAM.

FIG. 101 is an illustration of another example of coordinates of asignal point of a 2D NUC when a modulation scheme is 16QAM.

FIG. 102 is an illustration of another example of coordinates of asignal point of a 2D NUC when a modulation scheme is 64QAM.

FIG. 103 is an illustration of another example of coordinates of asignal point of a 2D NUC when a modulation scheme is 256QAM.

FIG. 104 is an illustration of another example of coordinates of asignal point of a 2D NUC when a modulation scheme is 256QAM.

FIG. 105 is a block diagram illustrating a configuration example of ablock interleaver 25.

FIG. 106 is an illustration of an example of the number C of columns ofparts 1 and 2 and part column lengths R1 and R2 for a combination of acode length N and a modulation scheme.

FIG. 107 is an illustration of block interleave performed by a blockinterleaver 25.

FIG. 108 is an illustration of group-wise interleave performed by agroup-wise interleaver 24.

FIG. 109 is an illustration of a 1st example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 110 is an illustration of a 2nd example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 111 is an illustration of a 3rd example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 112 is an illustration of a 4th example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 113 is an illustration of a 5th example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 114 is an illustration of a 6th example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 115 is an illustration of a 7th example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 116 is an illustration of an 8th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 117 is an illustration of a 9th example of a GW pattern for an LDPCcode in which a code length N is 64k bits.

FIG. 118 is an illustration of a 10th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 119 is an illustration of an 11th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 120 is an illustration of a 12th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 121 is an illustration of a 13th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 122 is an illustration of a 14th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 123 is an illustration of a 15th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 124 is an illustration of a 16th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 125 is an illustration of a 17th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 126 is an illustration of an 18th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 127 is an illustration of a 19th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 128 is an illustration of a 20th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 129 is an illustration of a 21st example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 130 is an illustration of a 22nd example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 131 is an illustration of a 23rd example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 132 is an illustration of a 24th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 133 is an illustration of a 25th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 134 is an illustration of a 26th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 135 is an illustration of a 27th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 136 is an illustration of a 28th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 137 is an illustration of a 29th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 138 is an illustration of a 30th example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 139 is an illustration of a 31st example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 140 is an illustration of a 32nd example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 141 is an illustration of a 33rd example of a GW pattern for anLDPC code in which a code length N is 64k bits.

FIG. 142 is an illustration of a 1st example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 143 is an illustration of a 2nd example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 144 is an illustration of a 3rd example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 145 is an illustration of a 4th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 146 is an illustration of a 5th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 147 is an illustration of a 6th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 148 is an illustration of a 7th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 149 is an illustration of an 8th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 150 is an illustration of a 9th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

FIG. 151 is an illustration of a 10th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 152 is an illustration of an 11th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 153 is an illustration of a 12th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 154 is an illustration of a 13th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 155 is an illustration of a 14th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 156 is an illustration of a 15th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 157 is an illustration of a 16th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

FIG. 158 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 159 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 160 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 161 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 162 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 163 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 164 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 165 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 166 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 167 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 168 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 169 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 170 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 171 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 172 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 173 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 174 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 175 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 176 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 177 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 178 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 179 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 180 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 181 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 182 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 183 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 184 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 185 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 186 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 187 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 188 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 189 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 190 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 191 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 192 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 193 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 194 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 195 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 196 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 197 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 198 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 199 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 200 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 201 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 202 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 203 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 204 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 205 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 206 is an illustration of a simulation result of a simulation ofmeasuring an error rate.

FIG. 207 is a block diagram illustrating a configuration example of areceiving device 12.

FIG. 208 is a block diagram illustrating a configuration example of abit deinterleaver 165.

FIG. 209 is a flowchart illustrating an example of a process performedby a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166.

FIG. 210 is an illustration of an example of a parity check matrix of anLDPC code.

FIG. 211 is an illustration of an example of a matrix (a transformedparity check matrix) obtained by performing a row permutation and acolumn permutation on a parity check matrix.

FIG. 212 is an illustration of an example of a transformed parity checkmatrix divided into 5×5 units.

FIG. 213 is a block diagram illustrating a configuration example of adecoding device that collectively performs P node operations.

FIG. 214 is a block diagram illustrating a configuration example of anLDPC decoder 166.

FIG. 215 is a block diagram illustrating a configuration example of ablock deinterleaver 54.

FIG. 216 is a block diagram illustrating another configuration exampleof a bit deinterleaver 165.

FIG. 217 is a block diagram illustrating a first configuration exampleof a reception system that can be applied to the receiving device 12.

FIG. 218 is a block diagram illustrating a second configuration exampleof a reception system that can be applied to the receiving device 12.

FIG. 219 is a block diagram illustrating a third configuration exampleof a reception system that can be applied to the receiving device 12.

FIG. 220 is a block diagram illustrating a configuration example of anembodiment of a computer to which the present technology is applied.

DESCRIPTION OF EMBODIMENTS

Hereinafter, exemplary embodiments of the present technology will bedescribed, but before the description of the exemplary embodiments ofthe present technology, an LDPC code will be described.

<LDPC Code>

The LDPC code is a linear code and it is not necessary for the LDPC codeto be a binary code. However, in this case, it is assumed that the LDPCcode is the binary code.

A maximum characteristic of the LDPC code is that a parity check matrixdefining the LDPC code is sparse. In this case, the sparse matrix is amatrix in which the number of “1” of elements of the matrix is verysmall (a matrix in which most elements are 0).

FIG. 1 is an illustration of an example of a parity check matrix H ofthe LDPC code.

In the parity check matrix H of FIG. 1, a weight of each column (thecolumn weight) (the number of “1”) becomes “3” and a weight of each row(the row weight) becomes “6”.

In encoding using the LDPC code (LDPC encoding), for example, ageneration matrix G is generated on the basis of the parity check matrixH and the generation matrix G is multiplied by binary information bits,so that a code word (LDPC code) is generated.

Specifically, an encoding device that performs the LDPC encoding firstcalculates the generation matrix G in which an expression GH^(T)=0 isrealized, between a transposed matrix H^(T) of the parity check matrix Hand the generation matrix G. In this case, when the generation matrix Gis a K×N matrix, the encoding device multiplies the generation matrix Gwith a bit string (vector u) of information bits including K bits andgenerates a code word c (=uG) including N bits. The code word (LDPCcode) that is generated by the encoding device is received at areception side through a predetermined communication path.

The LDPC code can be decoded by an algorithm called probabilisticdecoding suggested by Gallager, that is, a message passing algorithmusing belief propagation on a so-called Tanner graph, including avariable node (also referred to as a message node) and a check node.Hereinafter, the variable node and the check node are appropriatelyreferred to as nodes simply.

FIG. 2 is a flowchart illustrating a decoding sequence of an LDPC code.

Hereinafter, a real value (a reception LLR) that is obtained byrepresenting the likelihood of “0” of a value of an i-th code bit of theLDPC code (one code word) received by the reception side by a loglikelihood ratio is appropriately referred to as a reception valueu_(0i). In addition, a message output from the check node is referred toas u_(j) and a message output from the variable node is referred to asv_(i).

First, in decoding of the LDPC code, as illustrated in FIG. 2, in stepS11, the LDPC code is received, the message (check node message) u_(j)is initialized to “0”, and a variable k taking an integer as a counterof repetition processing is initialized to “0”, and the processingproceeds to step S12. In step S12, the message (variable node message)v_(i) is calculated by performing an operation (variable node operation)represented by an expression (1), on the basis of the reception valueuoi obtained by receiving the LDPC code, and the message u_(j) iscalculated by performing an operation (check node operation) representedby an expression (2), on the basis of the message v_(i).

$\begin{matrix}\left\lbrack {{Math}.\mspace{11mu} 1} \right\rbrack & \; \\{v_{i} = {u_{0\; i} + {\sum\limits_{j = 1}^{d_{v} - 1}u_{j}}}} & (1) \\\left\lbrack {{Math}.\mspace{11mu} 2} \right\rbrack & \; \\{{\tanh\left( \frac{u_{j}}{2} \right)} = {\prod\limits_{i = 1}^{d_{c} - 1}\;{\tanh\left( \frac{v_{i}}{2} \right)}}} & (2)\end{matrix}$

Here, d_(v) and d_(c) in an expression (1) and expression (2) arerespectively parameters which can be arbitrarily selected andillustrates the number of “1” in the longitudinal direction (column) andtransverse direction (row) of the parity check matrix H. For example, inthe case of an LDPC code ((3, 6) LDPC code) with respect to the paritycheck matrix H with a column weight of 3 and a row weight of 6 asillustrated in FIG. 1, d_(v)=3 and d_(c)=6 are established.

In the variable node operation of the expression (1) and the check nodeoperation of the expression (2), because a message input from an edge(line coupling the variable node and the check node) for outputting themessage is not an operation target, an operation range becomes 1 tod_(v)−1 or 1 to d_(c)−1. The check node operation of the expression (2)is performed actually by previously making a table of a function R (v₁,v₂) represented by an expression (3) defined by one output with respectto two inputs v₁ and v₂ and using the table consecutively (recursively),as represented by an expression (4).[Math. 3]x=2 tanh⁻¹{tanh(v ₁/2)tanh(v ₂/2)}=R(v ₁ ,v ₂)  (3)[Math. 4]u _(j) =R(v ₁ ,R(v ₂ ,R(v ₃ , . . . R(v _(d) _(o) ⁻² ,v _(d) _(o)⁻¹))))  (4)

In step S12, the variable k is incremented by “1” and the processingproceeds to step S13. In step S13, it is determined whether the variablek is more than the predetermined repetition decoding number of times C.When it is determined in step S13 that the variable k is not more thanC, the processing returns to step S12 and the same processing isrepeated hereinafter.

When it is determined in step S13 that the variable k is more than C,the processing proceeds to step S14, the message v_(i) that correspondsto a decoding result to be finally output is calculated by performing anoperation represented by an expression (5) and is output, and thedecoding processing of the LDPC code ends.

$\begin{matrix}\left\lbrack {{Math}.\mspace{11mu} 5} \right\rbrack & \; \\{v_{i} = {u_{0\; i} + {\sum\limits_{j = 1}^{d_{v}}u_{j}}}} & (5)\end{matrix}$

In this case, the operation of the expression (5) is performed usingmessages u_(j) from all edges connected to the variable node, differentfrom the variable node operation of the expression (1).

FIG. 3 illustrates an example of the parity check matrix H of the (3, 6)LDPC code (an encoding rate of 1/2 and a code length of 12).

In the parity check matrix H of FIG. 3, a weight of a column is set to 3and a weight of a row is set to 6, similar to FIG. 1.

FIG. 4 illustrates a Tanner graph of the parity check matrix H of FIG.3.

In FIG. 4, the check node is represented by “+” (plus) and the variablenode is represented by “=” (equal). The check node and the variable nodecorrespond to the row and the column of the parity check matrix H. Aline that couples the check node and the variable node is the edge andcorresponds to “1” of elements of the parity check matrix.

That is, when an element of a j-th row and an i-th column of the paritycheck matrix is 1, in FIG. 4, an i-th variable node (node of “=”) fromthe upper side and a j-th check node (node of “+”) from the upper sideare connected by the edge. The edge shows that a code bit correspondingto the variable node has a restriction condition corresponding to thecheck node.

In a sum product algorithm that is a decoding method of the LDPC code,the variable node operation and the check node operation arerepetitively performed.

FIG. 5 illustrates the variable node operation that is performed by thevariable node.

In the variable node, the message v_(i) that corresponds to the edge forcalculation is calculated by the variable node operation of theexpression (1) using messages u₁ and u₂ from the remaining edgesconnected to the variable node and the reception value u_(0i). Themessages that correspond to the other edges are also calculated by thesame method.

FIG. 6 illustrates the check node operation that is performed by thecheck node.

In this case, the check node operation of the expression (2) can berewritten by an expression (6) using a relation of an expressiona×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b). However, sign(x) is 1 in thecase of x≥0 and is −1 in the case of x<0.

$\begin{matrix}\left\lbrack {{Math}.\mspace{11mu} 6} \right\rbrack & \; \\\begin{matrix}{u_{j} = {2\;{\tanh^{- 1}\left( {\prod\limits_{i = 1}^{d_{c} - 1}\;{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}}} \\{= {2\;{\tanh^{- 1}\left\lbrack {\exp\left\{ {\sum\limits_{i = 1}^{d_{c} - 1}{\ln\left( {{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}} \right\} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}}} \right\rbrack}}} \\{= {2{\tanh^{- 1}\left\lbrack {\exp\left\{ {- \left( {\sum\limits_{i = 1}^{d_{c} - 1}{- {\ln\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}}} \right)} \right\}} \right\rbrack} \times}} \\{\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}\end{matrix} & (6)\end{matrix}$

In x≥0, if a function ϕ(x) is defined as an expressionϕ(x)=ln(tanh(x/2)), an expression ϕ⁻¹(x)=2 tanh⁻¹(e^(−x)) is realized.For this reason, the expression (6) can be changed to an expression (7).

$\begin{matrix}\left\lbrack {{Math}.\mspace{11mu} 7} \right\rbrack & \; \\{u_{j} = {{\phi^{- 1}\left( {\sum\limits_{i = 1}^{d_{c} - 1}{\phi\left( {v_{i}} \right)}} \right)} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}}} & (7)\end{matrix}$

In the check node, the check node operation of the expression (2) isperformed according to the expression (7).

That is, in the check node, as illustrated in FIG. 6, the message u_(j)that corresponds to the edge for calculation is calculated by the checknode operation of the expression (7) using messages v₁, v₂, v₃, v₄, andv₅ from the remaining edges connected to the check node. The messagesthat correspond to the other edges are also calculated by the samemethod.

The function ϕ(x) of the expression (7) can be represented asϕ(x)=ln((e^(x)+1)/(e^(x)−1)) and ϕ(x)=ϕ⁻¹(x) is satisfied in x>0. Whenthe functions ϕ(x) and ϕ⁻¹(x) are mounted to hardware, the functionsϕ(x) and ϕ⁻¹(x) may be mounted using an LUT (Look Up Table). However,both the functions ϕ(x) and ϕ⁻¹(x) become the same LUT.

<Configuration Example of Transmission System to which PresentDisclosure is Applied>

FIG. 7 illustrates a configuration example of an embodiment of atransmission system (a system means a logical gathering of a pluralityof devices and a device of each configuration may be arranged or may notbe arranged in the same casing) to which the present invention isapplied.

In FIG. 7, the transmission system includes a transmitting device 11 anda receiving device 12.

For example, the transmitting device 11 transmits (broadcasts)(transfers) a program of television broadcasting, and so on. That is,for example, the transmitting device 11 encodes target data that is atransmission target such as image data and audio data as a program intoLDPC codes, and, for example, transmits them through a communicationpath 13 such as a satellite circuit, a ground wave and a cable (wirecircuit).

The receiving device 12 receives the LDPC code transmitted from thetransmitting device 11 through the communication path 13, decodes theLDPC code to obtain the target data, and outputs the target data.

In this case, it is known that the LDPC code used by the transmissionsystem of FIG. 7 shows the very high capability in an AWGN (AdditiveWhite Gaussian Noise) communication path.

Meanwhile, in the communication path 13, burst error or erasure may begenerated. Especially in the case where the communication path 13 is theground wave, for example, in an OFDM (Orthogonal Frequency DivisionMultiplexing) system, power of a specific symbol may become 0 (erasure)according to delay of an echo (paths other than a main path), under amulti-path environment in which D/U (Desired to Undesired Ratio) is 0 dB(power of Undesired=echo is equal to power of Desired=main path).

In the flutter (communication path in which delay is 0 and an echohaving a Doppler frequency is added), when D/U is 0 dB, entire power ofan OFDM symbol at a specific time may become 0 (erasure) by the Dopplerfrequency.

In addition, the burst error may be generated due to a situation of awiring line from a receiving unit (not illustrated in the drawings) ofthe side of the receiving device 12 such as an antenna receiving asignal from the transmitting device 11 to the receiving device 12 orinstability of a power supply of the receiving device 12.

Meanwhile, in decoding of the LDPC code, in the variable nodecorresponding to the column of the parity check matrix H and the codebit of the LDPC code, as illustrated in FIG. 5, the variable nodeoperation of the expression (1) with the addition of (the receptionvalue u0i of) the code bit of the LDPC code is performed. For thisreason, if error is generated in the code bits used for the variablenode operation, precision of the calculated message is deteriorated.

In the decoding of the LDPC code, in the check node, the check nodeoperation of the expression (7) is performed using the messagecalculated by the variable node connected to the check node. For thisreason, if the number of check nodes in which error (including erasure)is generated simultaneously in (the code bits of the LDPC codescorresponding to) the plurality of connected variable nodes increases,decoding performance is deteriorated.

That is, if the two or more variable nodes of the variable nodesconnected to the check node become simultaneously erasure, the checknode returns a message in which the probability of a value being 0 andthe probability of a value being 1 are equal to each other, to all thevariable nodes. In this case, the check node that returns the message ofthe equal probabilities does not contribute to one decoding processing(one set of the variable node operation and the check node operation).As a result, it is necessary to increase the repetition number of timesof the decoding processing, the decoding performance is deteriorated,and consumption power of the receiving device 12 that performs decodingof the LDPC code increases.

Therefore, in the transmission system of FIG. 7, tolerance against theburst error or the erasure can be improved while performance in the AWGNcommunication path (AWGN channel) is maintained.

<Configuration Example of Transmitting Device 11>

FIG. 8 is a block diagram illustrating a configuration example of thetransmitting device 11 of FIG. 7.

In the transmitting device 11, one or more input streams correspondingto target data are supplied to a mode adaptation/multiplexer 111.

The mode adaptation/multiplexer 111 performs mode selection andprocesses such as multiplexing of one or more input streams suppliedthereto, as needed, and supplies data obtained as a result to a padder112.

The padder 112 performs necessary zero padding (insertion of Null) withrespect to the data supplied from the mode adaptation/multiplexer 111and supplies data obtained as a result to a BB scrambler 113.

The BB scrambler 113 performs base-band scrambling (BB scrambling) withrespect to the data supplied from the padder 112 and supplies dataobtained as a result to a BCH encoder 114.

The BCH encoder 114 performs BCH encoding with respect to the datasupplied from the BB scrambler 113 and supplies data obtained as aresult as LDPC target data to be an LDPC encoding target to an LDPCencoder 115.

The LDPC encoder 115 performs LDPC encoding according to a parity checkmatrix or the like in which a parity matrix to be a portioncorresponding to a parity bit of an LDPC code becomes a staircase (dualdiagonal) structure with respect to the LDPC target data supplied fromthe BCH encoder 114, for example, and outputs an LDPC code in which theLDPC target data is information bits.

That is, the LDPC encoder 115 performs the LDPC encoding to encode theLDPC target data with an LDPC such as the LDPC code (corresponding tothe parity check matrix) defined in the predetermined standard of theDVB-S.2, the DVB-T.2, the DVB-C.2 or the like, and the LDPC code(corresponding to the parity check matrix) or the like that is to beemployed in ATSC 3.0, and outputs the LDPC code obtained as a result.

The LDPC code defined in the standard of the DVB-T.2 and the LDPC codethat is to be employed in ATSC 3.0 are an IRA (Irregular RepeatAccumulate) code and a parity matrix of the parity check matrix of theLDPC code becomes a staircase structure. The parity matrix and thestaircase structure will be described later. The IRA code is describedin “Irregular Repeat-Accumulate Codes”, H. Jin, A. Khandekar, and R. J.McEliece, in Proceedings of 2nd International Symposium on Turbo codesand Related Topics, pp. 1-8, September 2000, for example.

The LDPC code that is output by the LDPC encoder 115 is supplied to thebit interleaver 116.

The bit interleaver 116 performs bit interleave to be described laterwith respect to the LDPC code supplied from the LDPC encoder 115 andsupplies the LDPC code after the bit interleave to an mapper 117.

The mapper 117 maps the LDPC code supplied from the bit interleaver 116to a signal point representing one symbol of orthogonal modulation in aunit (symbol unit) of code bits of one or more bits of the LDPC code andperforms the orthogonal modulation (multilevel modulation).

That is, the mapper 117 performs maps the LDPC code supplied from thebit interleaver 116 to a signal point determined by a modulation schemeperforming the orthogonal modulation of the LDPC code, on an IQ plane(IQ constellation) defined by an I axis representing an I component ofthe same phase as a carrier and a Q axis representing a Q componentorthogonal to the carrier, and performs the orthogonal modulation.

When the number of signal points decided in the modulation scheme of theorthogonal modulation performed by the mapper 117 is 2^(m), m-bit codebits of the LDPC code are used as a symbol (one symbol), and the mapper117 maps the LDPC code supplied from the bit interleaver 116 to a signalpoint indicating a symbol among the 2^(m) signal points in units ofsymbols.

Here, examples of the modulation scheme of the orthogonal modulationperformed by the mapper 117 include a modulation scheme specified in astandard such as DVB-T.2, a modulation scheme that is scheduled to beemployed in ATSC 3.0, and other modulation schemes, that is, includesBinary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK),8 Phase-Shift Keying (8PSK), 16 Amplitude Phase-Shift Keying (APSK),32APSK, 16 Quadrature Amplitude Modulation (QAM), 16QAM, 64QAM, 256QAM,1024QAM, 4096QAM, and 4 Pulse Amplitude Modulation (PAM). A modulationscheme by which the orthogonal modulation is performed in the mapper 117is set in advance, for example, according to an operation of an operatorof the transmitting device 11.

The data (a mapping result of mapping the symbol to the signal point)obtained by the process of the mapper 117 is supplied to a timeinterleaver 118.

The time interleaver 118 performs time interleave (interleave in a timedirection) in a unit of symbol with respect to the data supplied fromthe mapper 117 and supplies data obtained as a result to an single inputsingle output/multiple input single output encoder (SISO/MISO encoder)119.

The SISO/MISO encoder 119 performs spatiotemporal encoding with respectto the data supplied from the time interleaver 118 and supplies the datato the frequency interleaver 120.

The frequency interleaver 120 performs frequency interleave (interleavein a frequency direction) in a unit of symbol with respect to the datasupplied from the SISO/MISO encoder 119 and supplies the data to a framebuilder/resource allocation unit 131.

On the other hand, for example, control data (signalling) for transfercontrol such as BB signaling (Base Band Signalling) (BB Header) issupplied to the BCH encoder 121.

The BCH encoder 121 performs the BCH encoding with respect to thesignaling supplied thereto and supplies data obtained as a result to anLDPC encoder 122, similar to the BCH encoder 114.

The LDPC encoder 122 sets the data supplied from the BCH encoder 121 asLDPC target data, performs the LDPC encoding with respect to the data,and supplies an LDPC code obtained as a result to a mapper 123, similarto the LDPC encoder 115.

The mapper 123 maps the LDPC code supplied from the LDPC encoder 122 toa signal point representing one symbol of orthogonal modulation in aunit (symbol unit) of code bits of one or more bits of the LDPC code,performs the orthogonal modulation, and supplies data obtained as aresult to the frequency interleaver 124, similar to the mapper 117.

The frequency interleaver 124 performs the frequency interleave in aunit of symbol with respect to the data supplied from the mapper 123 andsupplies the data to the frame builder/resource allocation unit 131,similar to the frequency interleaver 120.

The frame builder/resource allocation unit 131 inserts symbols of pilotsinto necessary positions of the data (symbols) supplied from thefrequency interleavers 120 and 124, configures a frame (for example, aphysical layer (PL) frame, a T2 frame, a C2 frame, and so on) includingsymbols of a predetermined number from data (symbols) obtained as aresult, and supplies the frame to an OFDM generating unit 132.

The OFDM generating unit 132 generates an OFDM signal corresponding tothe frame from the frame supplied from the frame builder/resourceallocation unit 131 and transmits the OFDM signal through thecommunication path 13 (FIG. 7).

Here, for example, the transmitting device 11 can be configured withoutincluding part of the blocks illustrated in FIG. 8 such as the timeinterleaver 118, the SISO/MISO encoder 119, the frequency interleaver120 and the frequency interleaver 124.

<Configuration Example of Bit Interleaver 116>

FIG. 9 illustrates a configuration example of the bit interleaver 116 ofFIG. 8.

The bit interleaver 116 has a function of interleaving data, andincludes a parity interleaver 23, a group-wise interleaver 24, and ablock interleaver 25.

The parity interleaver 23 performs parity interleave for interleavingthe parity bits of the LDPC code supplied from the LDPC encoder 115 intopositions of other parity bits and supplies the LDPC code after theparity interleave to the group-wise interleaver 24.

The group-wise interleaver 24 performs the group-wise interleave withrespect to the LDPC code supplied from the parity interleaver 23 andsupplies the LDPC code after the group-wise interleave to the blockinterleaver 25.

Here, in the group-wise interleave, 360 bits of one segment are used asa bit group, where the LDPC code of one code is divided into segments inunits of 360 bits equal to the unit size P which will be describedlater, and the LDPC code supplied from the parity interleaver 23 isinterleaved in units of bit groups, starting from the head.

When the group-wise interleave is performed, the error rate can beimproved to be better than when the group-wise interleave is notperformed, and as a result, it is possible to secure the excellentcommunication quality in the data transmission.

The block interleaver 25 performs block interleave for demultiplexingthe LDPC code supplied from the group-wise interleaver 24, converts, forexample, the LDPC code corresponding to one code into an m-bit symbolserving as a unit of mapping, and supplies the m-bit symbol to themapper 117 (FIG. 8).

Here, in the block interleave, for example, the LDPC code correspondingto one code is converted into the m-bit symbol such that the LDPC codesupplied from the group-wise interleaver 24 is written in a storageregion in which columns serving as a storage region storing apredetermined number of bits in a column (vertical) direction arearranged in a row (horizontal) direction by the number m of bits of thesymbol in the column direction and read from the storage region in therow direction.

<Parity Check Matrix H of the LDPC Code>

Next, FIG. 10 illustrates an example of the parity check matrix H thatis used for LDPC encoding by the LDPC encoder 115 of FIG. 8.

The parity check matrix H becomes an LDGM (Low-Density GenerationMatrix) structure and can be represented by an expressionH=[H_(A)|H_(T)] (a matrix in which elements of the information matrixH_(A) are set to left elements and elements of the parity matrix H_(T)are set to right elements), using an information matrix H_(A) of aportion corresponding to information bits among the code bits of theLDPC code and a parity matrix H_(T) corresponding to the parity bits.

In this case, a bit number of the information bits among the code bitsof one code of LDPC code (one code word) and a bit number of the paritybits are referred to as an information length K and a parity length M,respectively, and a bit number of the code bits of one code (one codeword) of LDPC code is referred to as a code length N (=K+M).

The information length K and the parity length M of the LDPC code havingthe certain code length N are determined by an encoding rate. The paritycheck matrix H becomes a matrix in which row×column is M×N (a matrix ofM×N). The information matrix H_(A) becomes a matrix of M×K and theparity matrix H_(T) becomes a matrix of M×M.

FIG. 11 is an illustration of an example of the parity matrix H_(T) ofthe parity check matrix H used for LDPC encoding in the LDPC encoder 115of FIG. 8.

The parity matrix H_(T) of the parity check matrix H used for LDPCencoding in the LDPC encoder 115 is identical to, for example, theparity matrix H_(T) of the parity check matrix H of the LDPC codespecified in a standard such as DVB-T.2.

The parity matrix H_(T) of the parity check matrix H of the LDPC codethat is defined in the standard of the DVB-T.2 or the like becomes astaircase structure matrix (lower bidiagonal matrix) in which elementsof 1 are arranged in a staircase shape, as illustrated in FIG. 11. Therow weight of the parity matrix H_(T) becomes 1 with respect to thefirst row and becomes 2 with respect to the remaining rows. The columnweight becomes 1 with respect to the final column and becomes 2 withrespect to the remaining columns.

As described above, the LDPC code of the parity check matrix H in whichthe parity matrix H_(T) becomes the staircase structure can be easilygenerated using the parity check matrix H.

That is, the LDPC code (one code word) is represented by a row vector cand a column vector obtained by transposing the row vector isrepresented by C^(T). In addition, a portion of information bits of therow vector c to be the LDPC code is represented by a row vector A and aportion of the parity bits is represented by a row vector T.

The row vector c can be represented by an expression c=[A|T] (a rowvector in which elements of the row vector A are set to left elementsand elements of the row vector T are set to right elements), using therow vector A corresponding to the information bits and the row vector Tcorresponding to the parity bits.

In the parity check matrix H and the row vector c=[A|T] corresponding tothe LDPC code, it is necessary to satisfy an expression Hc^(T)=0. Therow vector T that corresponds to the parity bits constituting the rowvector c=[A|T] satisfying the expression Hc^(T)=0 can be sequentiallycalculated by setting elements of each row to 0, sequentially (in order)from elements of a first row of the column vector Hc^(T) in theexpression Hc^(T)=0, when the parity matrix H_(T) of the parity checkmatrix H=[H_(A)|H_(T)] becomes the staircase structure illustrated inFIG. 11.

FIG. 12 is an illustration of the parity check matrix H of the LDPC codethat is defined in the standard of the DVB-T.2 or the like.

The column weight becomes X with respect KX columns from a first columnof the parity check matrix H of the LDPC code defined in the standard ofthe DVB-T.2 or the like, becomes 3 with respect to the following K3columns, becomes 2 with respect to the following (M−1) columns, andbecomes 1 with respect to a final column.

In this case, KX+K3+M−1+1 is equal to the code length N.

FIG. 13 is an illustration of column numbers KX, K3, and M and a columnweight X, with respect to each encoding rate r of the LDPC code definedin the standard of the DVB-T.2 or the like.

In the standard of the DVB-T.2 or the like, LDPC codes that have codelengths N of 64800 bits and 16200 bits are defined.

With respect to the LDPC code having the code length N of 64800 bits, 11encoding rates (nominal rates) of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4,4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC codehaving the code length N of 16200 bits, 10 encoding rates of 1/4, 1/3,2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined.

Hereinafter, the code length N of the 64800 bits is referred to as 64kbits and the code length N of the 16200 is referred to as 16 kbits.

With respect to the LDPC code, an error rate tends to be lower in a codebit corresponding to a column of which a column weight of the paritycheck matrix H is large.

In the parity check matrix H that is illustrated in FIGS. 12 and 13 andis defined in the standard of the DVB-T.2 or the like, a column weightof a column of a head side (left side) tends to be large. Therefore,with respect to the LDPC code corresponding to the parity check matrixH, a code bit of a head side tends to be robust to error (there istolerance against the error) and a code bit of an ending side tends tobe weak for the error.

<Parity Interleave>

Next, the parity interleave by the parity interleaver 23 of FIG. 9 willbe described with reference to FIGS. 14 to 16.

FIG. 24 illustrates an example of (a part of) a Tanner graph of theparity check matrix of the LDPC code.

As illustrated in FIG. 14, if a plurality of, for example, two variablenodes among (the code bits corresponding to) the variable nodesconnected to the check node simultaneously become the error such as theerasure, the check node returns a message in which the probability of avalue being 0 and the probability of a value being 1 are equal to eachother, to all the variable nodes connected to the check node. For thisreason, if the plurality of variable nodes connected to the same checknode simultaneously become the erasure, decoding performance isdeteriorated.

Meanwhile, the LDPC code that is output by the LDPC encoder 115 of FIG.8 is an IRA code, same as the LDPC code that is defined in the standardof the DVB-T.2 or the like, and the parity matrix H_(T) of the paritycheck matrix H becomes a staircase structure, as illustrated in FIG. 11.

FIG. 15 illustrates the parity matrix H_(T) becoming the staircasestructure as illustrated in FIG. 11, and an example of a Tanner graphcorresponding to the parity matrix HT.

That is, A of FIG. 15 illustrates an example of the parity matrix HTbecoming the staircase structure and B of FIG. 15 illustrates the Tannergraph corresponding to the parity matrix HT of A of FIG. 15.

In the parity matrix H_(T) with a staircase structure, elements of 1 areadjacent in each row (excluding the first row). Therefore, in the Tannergraph of the parity matrix H_(T), two adjacent variable nodescorresponding to a column of two adjacent elements in which the value ofthe parity matrix H_(T) is 1 are connected with the same check node.

Therefore, when parity bits corresponding to two above-mentionedadjacent variable nodes become errors at the same time by burst errorand erasure, and so on, the check node connected with two variable nodes(variable nodes to find a message by the use of parity bits)corresponding to those two parity bits that became errors returnsmessage that the probability with a value of 0 and the probability witha value of 1 are equal probability, to the variable nodes connected withthe check node, and therefore the performance of decoding isdeteriorated. Further, when the burst length (bit number of parity bitsthat continuously become errors) becomes large, the number of checknodes that return the message of equal probability increases and theperformance of decoding is further deteriorated.

Therefore, the parity interleaver 23 (FIG. 9) performs the parityinterleave for interleaving the parity bits of the LDPC code from theLDPC encoder 115 into positions of other parity bits, to prevent thedecoding performance from being deteriorated.

FIG. 16 is an illustration of the parity matrix H_(T) of the paritycheck matrix H corresponding to the LDPC code that has undergone theparity interleave performed by the parity interleaver 23 of FIG. 9.

Here, the information matrix H_(A) of the parity check matrix Hcorresponding to the LDPC code output by the LDPC encoder 115 has acyclic structure, similarly to the information matrix of the paritycheck matrix H corresponding to the LDPC code specified in a standardsuch as DVB-T.2.

The cyclic structure refers to a structure in which a certain columnmatches one obtained by cyclically shifting another column, andincludes, for example, a structure in which a position of 1 of each rowof P columns becomes a position obtained by cyclically shifting a firstcolumn of the P columns in the column direction by a predetermined valuesuch as a value that is proportional to a value q obtained by dividing aparity length M for every P columns. Hereinafter, the P columns in thecyclic structure are referred to appropriately as a unit size.

As an LDPC code defined in a standard such as DVB-T.2, as described inFIG. 12 and FIG. 13, there are two kinds of LDPC codes whose code lengthN is 64800 bits and 16200 bits, and, for both of those two kinds of LDPCcodes, the unit size P is defined as 360 which is one of divisorsexcluding 1 and M among the divisors of the parity length M.

The parity length M becomes a value other than primes represented by anexpression M=q×P=q×360, using a value q different according to theencoding rate. Therefore, similar to the unit size P, the value q is oneother than 1 and M among the divisors of the parity length M and isobtained by dividing the parity length M by the unit size P (the productof P and q to be the divisors of the parity length M becomes the paritylength M).

As described above, when information length is assumed to be K, aninteger equal to or greater than 0 and less than P is assumed to be xand an integer equal to or greater than 0 and less than q is assumed tobe y, the parity interleaver 23 interleaves the K+qx+y+1-th code bitamong code bits of an LDPC code of N bits to the position of theK+Py+x+1-th code bit as parity interleave.

Since both of the K+qx+y+1-th code bit and the K+Py+x+1-th code bit arecode bits after the K+1-th one, they are parity bits, and therefore thepositions of the parity bits of the LDPC code are moved according to theparity interleave.

According to the parity interleave, (the parity bits corresponding to)the variable nodes connected to the same check node are separated by theunit size P, that is, 360 bits in this case. For this reason, when theburst length is less than 360 bits, the plurality of variable nodesconnected to the same check node can be prevented from simultaneouslybecoming the error. As a result, tolerance against the burst error canbe improved.

The LDPC code after the interleave for interleaving the (K+qx+y+1)-thcode bit into the position of the (K+Py+x+1)-th code bit is matched withan LDPC code of a parity check matrix (hereinafter, referred to as atransformed parity check matrix) obtained by performing columnreplacement for replacing the (K+qx+y+1)-th column of the originalparity check matrix H with the (K+Py+x+1)-th column.

In the parity matrix of the transformed parity check matrix, asillustrated in FIG. 16, a pseudo cyclic structure that uses the Pcolumns (in FIG. 16, 360 columns) as a unit appears.

Here, the pseudo cyclic structure is a structure in which the remainingportion excluding a part has the cyclic structure.

The transformed parity check matrix obtained by performing the columnpermutation corresponding to the parity interleave on the parity checkmatrix of the LDPC code specified in the standard such as DVB-T.2 hasthe pseudo cyclic structure rather than the (perfect) cyclic structuresince it is one 1 element short (it is a 0 element) in a portion (ashift matrix which will be described later) of a 360×360 matrix of aright top corner portion of the transformed parity check matrix.

The transformed parity check matrix for the parity check matrix of theLDPC code output by the LDPC encoder 115 has the pseudo cyclicstructure, for example, similarly to the transformed parity check matrixfor the parity check matrix of the LDPC code specified in the standardsuch as DVB-T.2.

The transformed parity check matrix of FIG. 16 becomes a matrix that isobtained by performing the column replacement corresponding to theparity interleave and replacement (row replacement) of a row toconfigure the transformed parity check matrix with a constitutive matrixto be described later, with respect to the original parity check matrixH.

FIG. 17 is a flowchart illustrating processing executed by the LDPCencoder 115, the bit interleaver 116, and the mapper 117 of FIG. 8.

The LDPC encoder 115 awaits supply of the LDPC target data from the BCHencoder 114. In step S101, the LDPC encoder 115 encodes the LDPC targetdata with the LDPC code and supplies the LDPC code to the bitinterleaver 116. The processing proceeds to step S102.

In step S102, the bit interleaver 116 performs the bit interleave on theLDPC code supplied from the LDPC encoder 115, and supplies the symbolobtained by the bit interleave to the mapper 117, and the processproceeds to step S103.

That is, in step S102, in the bit interleaver 116 (FIG. 9), the parityinterleaver 23 performs parity interleave with respect to the LDPC codesupplied from the LDPC encoder 115 and supplies the LDPC code after theparity interleave to the group-wise interleaver 24.

The group-wise interleaver 24 performs the group-wise interleave on theLDPC code supplied from the parity interleaver 23, and supplies theresulting LDPC code to the block interleaver 25.

The block interleaver 25 performs the block interleave on the LDPC codethat has undergone the group-wise interleave performed by the group-wiseinterleaver 24, and supplies the m-bit symbol obtained as a result tothe mapper 117.

In step S103, the mapper 117 maps the symbol supplied from the blockinterleaver 25 to any of the 2^(m) signal points decided in themodulation scheme of the orthogonal modulation performed by the mapper117, performs the orthogonal modulation, and supplies data obtained as aresult to the time interleaver 118.

As described above, by performing the parity interleave and thegroup-wise interleave, it is possible to improve the error rate whentransmission is performed using a plurality of code bits of the LDPCcode as one symbol.

Here, in FIG. 9, for the sake of convenience of description, the parityinterleaver 23 serving as the block performing the parity interleave andthe group-wise interleaver 24 serving as the block performing thegroup-wise interleave are configured individually, but the parityinterleaver 23 and the group-wise interleaver 24 may be configuredintegrally.

That is, both the parity interleave and the group-wise interleave can beperformed by writing and reading of the code bits with respect to thememory and can be represented by a matrix to convert an address (writeaddress) to perform writing of the code bits into an address (readaddress) to perform reading of the code bits.

Therefore, if a matrix obtained by multiplying a matrix representing theparity interleave and a matrix representing the group-wise interleave iscalculated, the code bits are converted by the matrixes, the parityinterleave is performed, and a group-wise interleave result of the LDPCcode after the parity interleave can be obtained.

In addition to the parity interleaver 23 and the group-wise interleaver24, the block interleaver 25 can be integrally configured.

That is, the block interleave executed by the block interleaver 25 canbe represented by the matrix to convert the write address of the memorystoring the LDPC code into the read address.

Therefore, if a matrix obtained by multiplying the matrix representingthe parity interleave, the matrix representing the group-wiseinterleave, and the matrix representing the block interleave iscalculated, the parity interleave, the group-wise interleave, and theblock interleave can be collectively executed by the matrixes.

<Configuration Example of LDPC Encoder 115>

FIG. 18 is a block diagram illustrating a configuration example of theLDPC encoder 115 of FIG. 8.

The LDPC encoder 122 of FIG. 8 is also configured in the same manner.

As described in FIGS. 12 and 13, in the standard of the DVB-T.2 or thelike, the LDPC codes that have the two code lengths N of 64800 bits and16200 bits are defined.

With respect to the LDPC code having the code length N of 64800 bits, 11encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and9/10 are defined. With respect to the LDPC code having the code length Nof 16200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4,4/5, 5/6, and 8/9 are defined (FIGS. 12 and 13).

For example, the LDPC encoder 115 can perform encoding (error correctionencoding) using the LDPC code of each encoding rate having the codelength N of 64800 bits or 16200 bits, according to the parity checkmatrix H prepared for each code length N and each encoding rate.

The LDPC encoder 115 includes an encoding processing unit 601 and astorage unit 602.

The encoding processing unit 601 includes an encoding rate setting unit611, an initial value table reading unit 612, a parity check matrixgenerating unit 613, an information bit reading unit 614, an encodingparity operation unit 615, an a control unit 616. The encodingprocessing unit 601 performs the LDPC encoding of LDPC target datasupplied to the LDPC encoder 115 and supplies an LDPC code obtained as aresult to the bit interleaver 116 (FIG. 8).

That is, the encoding rate setting unit 611 sets the code length N andthe encoding rate of the LDPC code, according to an operation of anoperator.

The initial value table reading unit 612 reads a parity check matrixinitial value table to be described later, which corresponds to the codelength N and the encoding rate set by the encoding rate setting unit611, from the storage unit 602.

The parity check matrix generating unit 613 generates a parity checkmatrix H by arranging elements of 1 of an information matrix H_(A)corresponding to an information length K (=information length N−paritylength M) according to the code length N and the encoding rate set bythe encoding rate setting unit 611 in the column direction with a periodof 360 columns (unit size P), on the basis of the parity check matrixinitial value table read by the initial value table reading unit 612,and stores the parity check matrix H in the storage unit 602.

The information bit reading unit 614 reads (extracts) information bitscorresponding to the information length K, from the LDPC target datasupplied to the LDPC encoder 115.

The encoding parity operation unit 615 reads the parity check matrix Hgenerated by the parity check matrix generating unit 613 from thestorage unit 602, and generates a code word (LDPC code) by calculatingparity bits for the information bits read by the information bit readingunit 614 on the basis of a predetermined expression using the paritycheck matrix H.

The control unit 616 controls each block constituting the encodingprocessing unit 601.

In the storage unit 602, a plurality of parity check matrix initialvalue tables that correspond to the plurality of encoding ratesillustrated in FIGS. 12 and 13, with respect to the code lengths N suchas the 64800 bits and 16200 bits, are stored. In addition, the storageunit 602 temporarily stores data that is necessary for processing of theencoding processing unit 601.

FIG. 19 is a flowchart illustrating an example of processing of the LDPCencoder 115 of FIG. 18.

In step S201, the encoding rate setting unit 611 determines (sets) thecode length N and the encoding rate r to perform the LDPC encoding.

In step S202, the initial value table reading unit 612 reads thepreviously determined parity check matrix initial value tablecorresponding to the code length N and the encoding rate r determined bythe encoding rate setting unit 611, from the storage unit 602.

In step S203, the parity check matrix generating unit 613 calculates(generates) the parity check matrix H of the LDPC code of the codelength N and the encoding rate r determined by the encoding rate settingunit 611, using the parity check matrix initial value table read fromthe storage unit 602 by the initial value table reading unit 612,supplies the parity check matrix to the storage unit 602, and stores theparity check matrix in the storage unit.

In step S204, the information bit reading unit 614 reads the informationbits of the information length K (=N×r) corresponding to the code lengthN and the encoding rate r determined by the encoding rate setting unit611, from the LDPC target data supplied to the LDPC encoder 115, readsthe parity check matrix H calculated by the parity check matrixgenerating unit 613 from the storage unit 602, and supplies theinformation bits and the parity check matrix to the encoding parityoperation unit 615.

In step S205, the encoding parity operation unit 615 sequentiallyoperates parity bits of a code word c that satisfies an expression (8)using the information bits and the parity check matrix H that have beenread from the information bit reading unit 614.Hc ^(T)=0  (8)

In the expression (8), c represents a row vector as the code word (LDPCcode) and c^(T) represents transposition of the row vector c.

As described above, when a portion of the information bits of the rowvector c as the LDPC code (one code word) is represented by a row vectorA and a portion of the parity bits is represented by a row vector T, therow vector c can be represented by an expression c=[A/T], using the rowvector A as the information bits and the row vector T as the paritybits.

In the parity check matrix H and the row vector c=[A|T] corresponding tothe LDPC code, it is necessary to satisfy an expression Hc^(T)=0. Therow vector T that corresponds to the parity bits constituting the rowvector c=[A|T] satisfying the expression Hc^(T)=0 can be sequentiallycalculated by setting elements of each row to 0, sequentially fromelements of a first row of the column vector Hc^(T) in the expressionHc^(T)=0, when the parity matrix H_(T) of the parity check matrixH=[H_(A)|H_(T)] becomes the staircase structure illustrated in FIG. 11.

If the encoding parity operation unit 615 calculates the parity bits Twith respect to the information bits A from the information bit readingunit 614, the encoding parity operation unit 615 outputs the code wordc=[A/T] represented by the information bits A and the parity bits T asan LDPC encoding result of the information bits A.

Then, in step S206, the control unit 616 determines whether the LDPCencoding ends. When it is determined in step S206 that the LDPC encodingdoes not end, that is, when there is LDPC target data to perform theLDPC encoding, the processing returns to step S201 (or step S204).Hereinafter, the processing of steps S201 (or step S204) to S206 isrepeated.

When it is determined in step S206 that the LDPC encoding ends, that is,there is no LDPC target data to perform the LDPC encoding, the LDPCencoder 115 ends the processing.

As described above, the parity check matrix initial value tablecorresponding to each code length N and each encoding rate r is preparedand the LDPC encoder 115 performs the LDPC encoding of the predeterminedcode length N and the predetermined encoding rate r, using the paritycheck matrix H generated from the parity check matrix initial valuetable corresponding to the predetermined code length N and thepredetermined encoding rate r.

<Example of the Parity Check Matrix Initial Value Table>

The parity check matrix initial value table is a table that representspositions of elements of 1 of the information matrix H_(A) (FIG. 10) ofthe parity check matrix H corresponding to the information length Kaccording to the code length N and the encoding rate r of the LDPC code(LDPC code defined by the parity check matrix H) for every 360 columns(unit size P) and is previously made for each parity check matrix H ofeach code length N and each encoding rate r.

That is, the parity check matrix initial value table represents at leastpositions of elements of 1 of the information matrix H_(A) for every 360columns (unit size P).

Examples of the parity check matrix H include a parity check matrix inwhich the (whole) parity matrix H_(T) has the staircase structure, whichis specified in DVB-T.2 or the like and a parity check matrix in which apart of the parity matrix H_(T) has the staircase structure, and theremaining portion is a diagonal matrix (a unit matrix), which isproposed by CRC/ETRI.

Hereinafter, an expression scheme of a parity check matrix initial valuetable indicating the parity check matrix in which the parity matrixH_(T) has the staircase structure, which is specified in DVB-T.2 or thelike, is referred to as a DVB scheme, and an expression scheme of aparity check matrix initial value table indicating the parity checkmatrix proposed by CRC/ETRI is referred to as an ETRI scheme.

FIG. 20 is an illustration of an example of the parity check matrixinitial value table in the DVB method.

That is, FIG. 20 illustrates a parity check matrix initial value tablewith respect to the parity check matrix H that is defined in thestandard of the DVB-T.2 and has the code length N of 16200 bits and theencoding rate (an encoding rate of notation of the DVB-T.2) r of 1/4.

The parity check matrix generating unit 613 (FIG. 18) calculates theparity check matrix H using the parity check matrix initial value tablein the DVB method, as follows.

FIG. 21 is an illustration of a method of calculating a parity checkmatrix H from a parity check matrix initial value table in the DVBmethod.

That I, FIG. 21 illustrates a parity check matrix initial value tablewith respect to the parity check matrix H that is defined in thestandard of the DVB-T.2 and has the code length N of 16200 bits and theencoding rate r of 2/3.

The parity check matrix initial value table in the DVB method is thetable that represents the positions of the elements of 1 of the wholeinformation matrix H_(A) corresponding to the information length Kaccording to the code length N and the encoding rate r of the LDPC codefor every 360 columns (unit size P). In the i-th row thereof, rownumbers (row numbers when a row number of a first row of the paritycheck matrix H is set to 0) of elements of 1 of a (1+360×(i−1)-th columnof the parity check matrix H are arranged by a number of column weightsof the (1+360×(i−1)-th column.

Here, since the parity matrix H_(T) (FIG. 10) corresponding to theparity length M in the parity check matrix H of the DVB scheme is fixedto the staircase structure illustrated in FIG. 15, it is possible toobtain the parity check matrix H if it is possible to obtain theinformation matrix H_(A) (FIG. 10) corresponding to the informationlength K through the parity check matrix initial value table.

A row number k+1 of the parity check matrix initial value table in theDVB method is different according to the information length K.

A relation of an expression (9) is realized between the informationlength K and the row number k+1 of the parity check matrix initial valuetable.K=(k+1)×360  (9)

In this case, 360 of the expression (9) is the unit size P described inFIG. 16.

In the parity check matrix initial value table of FIG. 21, 13 numericalvalues are arranged from the first row to the third row and 3 numericalvalues are arranged from the fourth row to the (k+1)-th row (in FIG. 21,the 30th row).

Therefore, the column weights of the parity check matrix H that arecalculated from the parity check matrix initial value table of FIG. 21are 13 from the first column to the (1+360×(3−1)−1)-th column and are 3from the (1+360×(3−1))-th column to the K-th column.

The first row of the parity check matrix initial value table of FIG. 21becomes 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451,4620, and 2622, which shows that elements of rows having row numbers of0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and2622 are 1 (and the other elements are 0), in the first column of theparity check matrix H.

The second row of the parity check matrix initial value table of FIG. 21becomes 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971,4358, and 3108, which shows that elements of rows having row numbers of1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and3108 are 1, in the 361 (=1+360×(2−1))-th column of the parity checkmatrix H.

As described above, the parity check matrix initial value tablerepresents positions of elements of 1 of the information matrix H_(A) ofthe parity check matrix H for every 360 columns.

The columns other than the (1+360×(i−1))-th column of the parity checkmatrix H, that is, the individual columns from the (2+360×(i−1))-thcolumn to the (360×i)-th column are arranged by cyclically shiftingelements of 1 of the (1+360×(i−1))-th column determined by the paritycheck matrix initial value table periodically in a downward direction(downward direction of the columns) according to the parity length M.

That is, the (2+360×(i−1))-th column is obtained by cyclically shifting(1+360×(i−1))-th column in the downward direction by M/360 (=q) and thenext (3+360×(i−1))-th column is obtained by cyclically shifting(1+360×(i−1))-th column in the downward direction by 2×M/360 (=2×q)(obtained by cyclically shifting (2+360×(i−1))-th column in the downwarddirection by M/360 (=q)).

If a numerical value of a j-th column (j-th column from the left side)of an i-th row (i-th row from the upper side) of the parity check matrixinitial value table is represented as h_(i,j) and a row number of thej-th element of 1 of the w-th column of the parity check matrix H isrepresented as H_(w)j, the row number H_(w-j) of the element of 1 of thew-th column to be a column other than the (1+360×(i−1))-th column of theparity check matrix H can be calculated by an expression (10).H _(w-j)=mod{h _(i,j)+mod((w−1),P)×q,M)  (10)

In this case, mod(x, y) means a remainder that is obtained by dividing xby y.

In addition, P is a unit size described above. In the presentembodiment, for example, same as the standard of the DVB-S.2, theDVB-T.2, and the DVB-C.2, P is 360. In addition, q is a value M/360 thatis obtained by dividing the parity length M by the unit size P (=360).

The parity check matrix generating unit 613 (FIG. 18) specifies the rownumbers of the elements of 1 of the (1+360×(i−1))-th column of theparity check matrix H by the parity check matrix initial value table.

The parity check matrix generating unit 613 (FIG. 18) calculates the rownumber H_(w-j) of the element of 1 of the w-th column to be the columnother than the (1+360×(i−1))-th column of the parity check matrix H,according to the expression (10), and generates the parity check matrixH in which the element of the obtained row number is set to 1.

FIG. 22 is an illustration of a structure of the parity check matrix ofthe ETRI scheme.

The parity check matrix of the ETRI scheme is configured with an Amatrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

The A matrix is a g×K upper left matrix of the parity check matrixexpressed by a predetermined value g and the information length K of theLDPC code (=the code length N×the encoding rate r).

The B matrix is a g×g matrix having the staircase structure adjacent tothe right of the A matrix.

The C matrix is an (N−K−g)×(K+g) matrix adjacently below the A matrixand the B matrix.

The D matrix is an (N−K−g)×(N−K−g) unit matrix adjacent to the right ofthe C matrix.

The Z matrix is a g×(N−K−g) zero matrix (zero matrix) adjacent to theright of the B matrix.

In the parity check matrix of the ETRI scheme configured with the A to Dmatrices and the Z matrix, the A matrix and a portion of the C matrixconfigure an information matrix, and the B matrix, the remaining portionof the C matrix, the D matrix, and the Z matrix configure a paritymatrix.

Further, since the B matrix is the matrix having the staircasestructure, and the D matrix is the unit matrix, a portion (a portion ofthe B matrix) of the parity matrix of the parity check matrix of theETRI scheme has the staircase structure, and the remaining portion (theportion of the D matrix) is the diagonal matrix (the unit matrix).

Similarly to the information matrix of the parity check matrix of theDVB scheme, the A matrix and the C matrix have the cyclic structure forevery 360 columns (the unit size P), and the parity check matrix initialvalue table of the ETRI scheme indicates positions of 1 elements of theA matrix and the C matrix in units of 360 columns.

Here, as described above, since the A matrix, and a portion of the Cmatrix configure the information matrix, it can be said that the paritycheck matrix initial value table of the ETRI scheme that indicatespositions of 1 elements of the A matrix and the C matrix in units of 360columns indicates at least positions of 1 elements of the informationmatrix in units of 360 columns.

FIG. 23 is an illustration of an example of the parity check matrixinitial value table of the ETRI scheme.

In other words, FIG. 23 illustrates an example of a parity check matrixinitial value table for a parity check matrix in which the code length Nis 50 bits, and the encoding rate r is 1/2.

The parity check matrix initial value table of the ETRI scheme is atable in which positions of 1 elements of the A matrix and the C matrixare indicated for each unit size P, and row numbers (row numbers when arow number of a first row of the parity check matrix is 0) of 1 elementsof a (1+P×(i−1))-th column of the parity check matrix that correspond innumber to the column weight of the (1+P×(i−1))-th column are arranged inan i-th row.

Here, in order to simplify the description, the unit size P is assumedto be, for example, 5.

Further, parameters for the parity check matrix of the ETRI schemeinclude g=M₁, M₂, Q₁, and Q₂.

g=M₁ is a parameter for deciding the size of the B matrix and has avalue that is a multiple of the unit size P. The performance of the LDPCcode is changed by adjusting g=M₁, and g=M₁ is adjusted to apredetermined value when the parity check matrix is decided. Here, 15,which is three times the unit size P (=5), is assumed to be employed asg=M₁.

M₂ has a value M−M₁ obtained by subtracting M₁ from the parity length M.

Here, since the information length K is N×r=50×½=25, and the paritylength M is N−K=50−25=25, M₂ is M−M₁=25−15=10.

Q₁ is obtained from the formula Q₁=M₁/P, and indicates the number ofshifts (the number of rows) of the cyclic shift in the A matrix.

In other words, in each column other than the (1+P×(i−1))-th column ofthe A matrix of the parity check matrix of the ETRI scheme, that is, ineach of a (2+P×(i−1))-th column to a (P×i)-th column, 1 elements of a(1+360×(i−1))-th column decided by the parity check matrix initial valuetable have periodically been cyclically shifted downward (downward inthe column) and arranged, and Q₁ indicates the number of shifts thecyclic shift in the A matrix.

Q₂ is obtained from the formula Q₂=M₂/P, and indicates the number ofshifts (the number of rows) of the cyclic shift in the C matrix.

In other words, in each column other than the (1+P×(i−1))-th column ofthe C matrix of the parity check matrix of the ETRI scheme, that is, ineach of a (2+P×(i−1))-th column to a (P×i)-th column, 1 elements of a(1+360×(i−1))-th column decided by the parity check matrix initial valuetable have periodically been cyclically shifted downward (downward inthe column) and arranged, and Q₂ indicates the number of shifts thecyclic shift in the C matrix.

Here, Q₁ is M₁/P=15/5=3, and Q₂ is M₂/P=10/5=2.

In the parity check matrix initial value table of FIG. 23, 3 numericalvalues are arranged in 1st and 2nd rows, and one numerical value isarranged in 3rd to 5th rows, and according to a sequence of thenumerical values, the column weight of the parity check matrix obtainedfrom the parity check matrix initial value table of FIG. 23 is 3 in the1st column to a (1+5×(2−1)−1)-th column and 1 in a (1+5×(2−1))-th columnto a 5th column.

In other words, 2, 6, and 18 are arranged in the 1st row of the paritycheck matrix initial value table of FIG. 23, which indicates thatelements of rows having the row numbers of 2, 6, and 18 are 1 (and theother elements are 0) in the 1st column of the parity check matrix.

Here, in this case, the A matrix is a 15×25 (g×K) matrix, the C matrixis a 10×40 ((N−K−g)×(K+g)) matrix, rows having the row numbers of 0 to14 in the parity check matrix are rows of the A matrix, and rows havingthe row numbers of 15 to 24 in the parity check matrix are rows of the Cmatrix.

Thus, among the rows having the row numbers of 2, 6, and 18 (hereinafterreferred to as rows #2, #6, and #18), the rows #2 and #6 are the rows ofthe A matrix, and the row #18 is the row of the C matrix.

2, 10, and 19 are arranged in the 2nd row of the parity check matrixinitial value table of FIG. 23, which indicates that elements of therows #2, #10, and #19 are 1 in a 6 (=1+5×(2−1))-th column of the paritycheck matrix.

Here, in the 6 (=1+5×(2−1))-th column of the parity check matrix, amongthe rows #2, #10, and #19, the rows #2 and #10 are the rows of the Amatrix, and the row #19 is the row of the C matrix.

22 is arranged in the 3rd row of the parity check matrix initial valuetable of FIG. 23, which indicates that an element of the row #22 is 1 inan 11 (=1+5×(3−1))-th column of the parity check matrix.

Here, in the 11 (=1+5×(3−1))-th column of the parity check matrix, therow #22 is the row of the C matrix.

Similarly, 19 in the 4th column of the parity check matrix initial valuetable of FIG. 23 indicates that an element of the row #19 is 1 in a 16(=1+5×(4−1))-th column of the parity check matrix, and 15 in the 5th rowof the parity check matrix initial value table of FIG. 23 indicates thatan element of the row #15 is 1 in a 21(=1+5×(5−1))-st column of theparity check matrix.

As described above, the parity check matrix initial value tableindicates the positions of the 1 elements of the A matrix and the Cmatrix of the parity check matrix for each unit size P (=5 columns).

In each column other than a (1+5×(i−1))-th column of the A matrix andthe C matrix of the parity check matrix, that is, in each of a(2+5×(i−1))-th column to a (5×i)-th column, the 1 elements of the(1+5×(i−1))-th column decided by the parity check matrix initial valuetable have periodically been cyclically shifted downward (downward inthe column) and arranged according to the parameters Q₁ and Q₂.

In other words, for example, in the (2+5×(i−1))-th column of the Amatrix, the (1+5×(i−1))-th column has been cyclically shifted downwardby Q₁ (=3), and in a (3+5×(i−1))-th column, the (1+5×(i−1))-th columnhas been cyclically shifted downward by 2×Q₁ (=2×3) (the (2+5×(i−1))-thcolumn has been cyclically shifted downward by Q₁).

Further, for example, in the (2+5×(i−1))-th column of the C matrix, the(1+5×(i−1))-th column has been cyclically shifted downward by Q₂ (=2),and in a (3+5×(i−1))-th column, the (1+5×(i−1))-th column has beencyclically shifted downward by 2×Q₂ (=2×2) (the (2+5×(i−1))-th columnhas been cyclically shifted downward by Q₂).

FIG. 24 is an illustration of the A matrix generated from the paritycheck matrix initial value table of FIG. 23.

In the A matrix of FIG. 24, according to the 1 st row of the paritycheck matrix initial value table of FIG. 23, elements of rows #2 and #6of a 1 (=1+5×(1−1))-st column are 1.

Further, in each of a 2 (=2+5×(1−1))-nd column to a 5 (=5+5×(1−1))-thcolumn, an immediately previous column has been cyclically shifteddownward by Q₁=3.

Further, in the A matrix of FIG. 24, according to the 2nd row of theparity check matrix initial value table of FIG. 23, elements of rows #2and #10 of a 6 (=1+5×(2−1))-th column are 1.

Further, in each of a 7 (=2+5×(2−1))-th column to a 10 (=5+5×(2−1))-thcolumn, an immediately previous column has been cyclically shifteddownward by Q₁=3.

FIG. 25 is an illustration of the parity interleave of the B matrix.

The parity check matrix generating unit 613 (FIG. 18) generates the Amatrix using the parity check matrix initial value table, and arrangesthe B matrix having the staircase structure at the right of the Amatrix. Further, the parity check matrix generating unit 613 regards theB matrix as the parity matrix, and performs the parity interleave sothat the adjacent 1 elements of the B matrix having the staircasestructure are away from each other in the row direction by the unit sizeP=5.

FIG. 25 illustrates the A matrix and the B matrix after the B matrix hasundergone the parity interleave.

FIG. 26 is an illustration of the C matrix generated from the paritycheck matrix initial value table of FIG. 23.

In the C matrix of FIG. 26, according to the 1st row of the parity checkmatrix initial value table of FIG. 23, element of a row #18 of a 1(=1+5×(1−1))-st column of the parity check matrix is 1.

Further, each of a 2 (=2+5×(1−1))-nd column to a 5 (=5+5×(1−1))-thcolumn is one in which an immediately previous column has beencyclically shifted downward by Q₂=2.

Further, in the C matrix of FIG. 26, according to the 2nd to 5th columnsof the parity check matrix initial value table of FIG. 23, elements of arow #19 of a 6 (=1+5×(2−1))-th column of the parity check matrix, a row#22 of an 11 (=1+5×(3−1))-th column, a row #19 of a 16 (=1+5×(4−1))-thcolumn, and a row #15 of a 21 (=1+5×(5−1))-th column are 1.

Further, in each of the 7 (=2+5×(2−1))-th column to the 10(=5+5×(2−1))-th column, each of a 12 (=2+5×(3−1))-th column to a 15(=5+5×(3−1))-th column, each of a 17 (=2+5×(4−1))-th column to a 20(=5+5×(4−1))-th column, and each of a 22 (=2+5×(5−1))-nd column to a 25(=5+5×(5−1))-th column, an immediately previous column has beencyclically shifted downward by Q₂=2.

The parity check matrix generating unit 613 (FIG. 18) generates the Cmatrix using the parity check matrix initial value table, and arrangesthe C matrix below the A matrix and the B matrix (that has undergone theparity interleave).

Further, the parity check matrix generating unit 613 arranges the Zmatrix at the right of the B matrix, arranges the D matrix at the rightof the C matrix, and generates the parity check matrix illustrated inFIG. 26.

FIG. 27 is an illustration of the parity interleave of the D matrix.

After generating the parity check matrix of FIG. 26, the parity checkmatrix generating unit 613 regards the D matrix as the parity matrix,and performs the parity interleave (only for the D matrix) so that the 1elements of the odd-numbered rows and the next even-numbered rows of theD matrix of the unit matrix are away from each other in the rowdirection by the unit size P (=5).

FIG. 27 illustrates the parity check matrix after the parity interleaveof the D matrix is performed on the parity check matrix of FIG. 26.

(The encoding parity operation unit 615 (FIG. 18) of) The LDPC encoder115 performs LDPC encoding (generation of the LDPC code), for example,using the parity check matrix of FIG. 27.

Here, the LDPC code generated using the parity check matrix of FIG. 27is the LDPC code that has undergone the parity interleave, and thus itis unnecessary to perform the parity interleave on the LDPC codegenerated using the parity check matrix of FIG. 27 in the parityinterleaver 23 (FIG. 9).

FIG. 28 is an illustration of the parity check matrix obtained byperforming the column permutation serving as the parity deinterleave forrestoring the parity interleave to an original state on the B matrix,the portion of the C matrix (the portion of the C matrix arranged belowthe B matrix), and the D matrix of the parity check matrix of FIG. 27.

The LDPC encoder 115 can perform LDPC encoding (generation of the LDPCcode) using the parity check matrix of FIG. 28.

When the LDPC encoding is performed using the parity check matrix ofFIG. 28, the LDPC code that does not undergo the parity interleave isobtained according to the LDPC encoding. Thus, when the LDPC encoding isperformed using the parity check matrix of FIG. 28, the parityinterleaver 23 (FIG. 9) performs the parity interleave.

FIG. 29 is an illustration of the transformed parity check matrixobtained by performing the row permutation on the parity check matrix ofFIG. 27.

As will be described later, the transformed parity check matrix is amatrix represented by a combination of a P×P unit matrix, a quasi unitmatrix obtained by setting one or more is of the unit matrix to zero(0), a shift matrix obtained by cyclically shifting the unit matrix orthe quasi unit matrix, a sum matrix serving as a sum of two or morematrices of the unit matrix, the quasi unit matrix, and the shiftedmatrix, and a P×P zero matrix.

As the transformed parity check matrix is used for decoding of the LDPCcode, an architecture of performing P check node operations and Pvariable node operations at the same time can be employed for decodingthe LDPC code as will be described later.

<New LDPC Code>

Incidentally, a terrestrial digital television broadcasting standardcalled ATSC 3.0 is currently pending.

In this regard, a novel LDPC code which can be used in ATSC 3.0 andother data transmission (hereinafter referred to as a new LDPC code)will be described.

For example, the LDPC code of the DVB scheme or the LDPC code of theETRI scheme having the unit size P of 360, similarly to DVB-T.2 or thelike, and corresponding to the parity check matrix having the cyclicstructure can be employed as the new LDPC code.

The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC encoding forgenerating a new LDPC code using the parity check matrix obtained fromthe parity check matrix initial value table of the new LDPC code inwhich the code length N is 16 kbits or 64 kbits, and the encoding rate ris any of 5/15, 6,15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, and 13/15.

In this case, the storage unit 602 of the LDPC encoder 115 (FIG. 8)stores the parity check matrix initial value of the new LDPC code.

FIG. 30 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 8/15 (hereinafter, also referred to as Sony symbol (16k, 8/15)),proposed by the applicant of the present application.

FIG. 31 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 10/15 (hereinafter, also referred to as Sony symbol (16k, 10/15)),proposed by the applicant of the present application.

FIG. 32 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 12/15 (hereinafter, also referred to as Sony symbol (16k, 12/15)),proposed by the applicant of the present application.

FIGS. 33, 34, and 35 are illustrations of an example of a parity checkmatrix initial value table of the DVB scheme for a parity check matrixof a new LDPC code in which the code length N is 64 kbits, and theencoding rate r is 7/15 (hereinafter, also referred to as Sony symbol(64k, 7/15)), proposed by the applicant of the present application.

FIG. 34 is an illustration subsequent to FIG. 33, and FIG. 35 is anillustration subsequent to FIG. 34.

FIGS. 36, 37, and 38 are illustrations of an example of a parity checkmatrix initial value table of the DVB scheme for a parity check matrixof a new LDPC code in which the code length N is 64 kbits, and theencoding rate r is 9/15 (hereinafter, also referred to as Sony symbol(64k, 9/15)), proposed by the applicant of the present application.

FIG. 37 is an illustration subsequent to FIG. 36, and FIG. 38 is anillustration subsequent to FIG. 37.

FIGS. 39, 40, 41, and 42 are illustrations of an example of a paritycheck matrix initial value table of the DVB scheme for a parity checkmatrix of a new LDPC code in which the code length N is 64 kbits, andthe encoding rate r is 11/15 (hereinafter, also referred to as Sonysymbol (64k, 11/15)), proposed by the applicant of the presentapplication.

FIG. 40 is an illustration subsequent to FIG. 39, and FIG. 41 is anillustration subsequent to FIG. 40.

FIGS. 43, 44, 45, and 46 are illustrations of an example of a paritycheck matrix initial value table of the DVB scheme for a parity checkmatrix of a new LDPC code in which the code length N is 64 kbits, andthe encoding rate r is 13/15 (hereinafter, also referred to as Sonysymbol (64k, 13/15)), proposed by the applicant of the presentapplication.

FIG. 44 is an illustration subsequent to FIG. 43, and FIG. 45 is anillustration subsequent to FIG. 44.

FIGS. 47 and 48 are illustrations of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 64 kbits, and the encoding rater is 6/15 (hereinafter, also referred to as Samsung symbol (64k, 6/15)),proposed by Samsung.

FIG. 48 is an illustration subsequent to FIG. 47.

FIGS. 49, 50, and 51 are illustrations of an example of a parity checkmatrix initial value table of the DVB scheme for a parity check matrixof a new LDPC code in which the code length N is 64 kbits, and theencoding rate r is 8/15 (hereinafter, also referred to as Samsung symbol(64k, 8/15)), proposed by Samsung.

FIG. 50 is an illustration subsequent to FIG. 49, and FIG. 51 is anillustration subsequent to FIG. 50.

FIGS. 52, 53, and 54 are illustrations of an example of a parity checkmatrix initial value table of the DVB scheme for a parity check matrixof a new LDPC code in which the code length N is 64 kbits, and theencoding rate r is 12/15 (hereinafter, also referred to as Samsungsymbol (64k, 12/15)), proposed by Samsung.

FIG. 53 is an illustration subsequent to FIG. 52, and FIG. 54 is anillustration subsequent to FIG. 53.

FIG. 55 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 6/15 (hereinafter, also referred to as LGE symbol (16k, 6/15)),proposed by LG Electronics Inc.

FIG. 56 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 7/15 (hereinafter, also referred to as LGE symbol (16k, 7/15)),proposed by LG Electronics Inc.

FIG. 57 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 9/15 (hereinafter, also referred to as LGE symbol (16k, 9/15)),proposed by LG Electronics Inc.

FIG. 58 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 11/15 (hereinafter, also referred to as LGE symbol (16k, 11/15)),proposed by LG Electronics Inc.

FIG. 59 is an illustration of an example of a parity check matrixinitial value table of the DVB scheme for a parity check matrix of a newLDPC code in which the code length N is 16 kbits, and the encoding rater is 13/15 (hereinafter, also referred to as LGE symbol (16k, 13/15)),proposed by LG Electronics Inc.

FIGS. 60, 61, and 62 are an illustrations of an example of a paritycheck matrix initial value table of the DVB scheme for a parity checkmatrix of a new LDPC code in which the code length N is 64 kbits, andthe encoding rate r is 10/15 (hereinafter, also referred to as LGEsymbol (64k, 10/15)), proposed by LG Electronics Inc.

FIG. 61 is an illustration subsequent to FIG. 60, and FIG. 62 is anillustration subsequent to FIG. 61.

FIGS. 63, 64, and 65 are illustrations of an example of a parity checkmatrix initial value table of the DVB scheme for a parity check matrixof a new LDPC code in which the code length N is 64 kbits, and theencoding rate r is 9/15 (hereinafter, also referred to as NERC symbol(64k, 9/15)), proposed by NERC.

FIG. 64 is an illustration subsequent to FIG. 63, and FIG. 65 is anillustration subsequent to FIG. 64.

FIG. 66 is an illustration of an example of a parity check matrixinitial value table of the ETRI scheme for a parity check matrix of anew LDPC code in which the code length N is 16 kbits, and the encodingrate r is 5/15 (hereinafter, also referred to as ETRI symbol (16k,5/15)), proposed by CRC/ETRI.

FIGS. 67 and 68 are illustrations of an example of a parity check matrixinitial value table of the ETRI scheme for a parity check matrix of anew LDPC code in which the code length N is 64 kbits, and the encodingrate r is 5/15 (hereinafter, also referred to as ETRI symbol (64k,5/15)), proposed by CRC/ETRI.

FIG. 68 is an illustration subsequent to FIG. 67.

FIGS. 69 and 70 are illustrations of an example of a parity check matrixinitial value table of the ETRI scheme for a parity check matrix of anew LDPC code in which the code length N is 64 kbits, and the encodingrate r is 6/15 (hereinafter, also referred to as ETRI symbol (64k,6/15)), proposed by CRC/ETRI.

FIG. 70 is an illustration subsequent to FIG. 69.

FIGS. 71 and 72 are illustrations of an example of a parity check matrixinitial value table of the ETRI scheme for a parity check matrix of anew LDPC code in which the code length N is 64 kbits, and the encodingrate r is 7/15 (hereinafter, also referred to as ETRI symbol (64k,7/15)), proposed by CRC/ETRI.

FIG. 72 is an illustration subsequent to FIG. 71.

Among the new LDPC codes, the Sony symbol is an LDPC code havingparticularly excellent performance.

Here, the LDPC code of good performance is an LDPC code obtained from anappropriate parity check matrix H.

The appropriate parity check matrix H is, for example, a parity checkmatrix that satisfies a predetermined condition to make BER (and FER)smaller when an LDPC code obtained from the parity check matrix H istransmitted at low E_(s)/N₀ or E_(b)/N₀ (signal-to-noise power ratio perbit).

For example, the appropriate parity check matrix H can be found byperforming simulation to measure BER when LDPC codes obtained fromvarious parity check matrices that satisfy a predetermined condition aretransmitted at low E_(s)/N₀.

As a predetermined condition to be satisfied by the appropriate paritycheck matrix H, for example, an analysis result obtained by a codeperformance analysis method called density evolution (Density Evolution)is excellent, and a loop of elements of 1 does not exist, which iscalled cycle 4, and so on.

Here, in the information matrix H_(A), it is known that the decodingperformance of LDPC code is deteriorated when elements of 1 are denselike cycle 4, and therefore it is requested that cycle 4 does not exist,as a predetermined condition to be satisfied by the appropriate paritycheck matrix H.

Here, the predetermined condition to be satisfied by the appropriateparity check matrix H can be arbitrarily determined from the viewpointof the improvement in the decoding performance of LDPC code and thefacilitation (simplification) of decoding processing of LDPC code, andso on.

FIG. 73 and FIG. 74 are diagrams to describe the density evolution thatcan obtain an analytical result as a predetermined condition to besatisfied by the appropriate parity check matrix H.

The density evolution is a code analysis method that calculates theexpectation value of the error probability of the entire LDPC code(ensemble) with a code length N of ∞ characterized by a degree sequencedescribed later.

For example, when the dispersion value of noise is gradually increasedfrom 0 on the AWGN channel, the expectation value of the errorprobability of a certain ensemble is 0 first, but, when the dispersionvalue of noise becomes equal to or greater than a certain threshold, itis not 0.

According to the density evolution, by comparison of the threshold ofthe dispersion value of noise (which may also be called a performancethreshold) in which the expectation value of the error probability isnot 0, it is possible to decide the quality of ensemble performance(appropriateness of the parity check matrix).

Here, as for a specific LDPC code, when an ensemble to which the LDPCcode belongs is decided and density evolution is performed for theensemble, rough performance of the LDPC code can be expected.

Therefore, if an ensemble of good performance is found, an LDPC code ofgood performance can be found from LDPC codes belonging to the ensemble.

Here, the above-mentioned degree sequence shows at what percentage avariable node or check node having the weight of each value exists withrespect to the code length N of an LDPC code.

For example, a regular (3,6) LDPC code with an encoding rate of 1/2belongs to an ensemble characterized by a degree sequence in which theweight (column weight) of all variable nodes is 3 and the weight (rowweight) of all check nodes is 6.

FIG. 73 illustrates a Tanner graph of such an ensemble.

In the Tanner graph of FIG. 73, there are variable nodes shown bycircles (sign O) in the diagram only by N pieces equal to the codelength N, and there are check nodes shown by quadrangles (sign Q) onlyby N/2 pieces equal to a multiplication value multiplying encoding rate1/2 by the code length N.

Three branches (edge) equal to the column weight are connected with eachvariable node, and therefore there are totally 3N branches connectedwith N variable nodes.

Moreover, six branches (edge) equal to the row weight are connected witheach check node, and therefore there are totally 3N branches connectedwith N/2 check nodes.

In addition, there is one interleaver in the Tanner graph in FIG. 73.

The interleaver randomly rearranges 3N branches connected with Nvariable nodes and connects each rearranged branch with any of 3Nbranches connected with N/2 check nodes.

There are (3N)! (=(3N)×(3N−1)× . . . ×1) rearrangement patterns torearrange 3N branches connected with N variable nodes in theinterleaver. Therefore, an ensemble characterized by the degree sequencein which the weight of all variable nodes is 3 and the weight of allcheck nodes is 6, becomes aggregation of (3N)!LDPC codes.

In simulation to find an LDPC code of good performance (appropriateparity check matrix), an ensemble of a multi-edge type is used in thedensity evolution.

In the multi edge type, an interleaver through which the branchesconnected with the variable nodes and the branches connected with thecheck nodes pass, is divided into plural (multi edge), and, by thismeans, the ensemble is characterized more strictly.

FIG. 74 illustrates an example of a Tanner graph of an ensemble of themulti-edge type.

In the Tanner graph of FIG. 74, there are two interleavers of the firstinterleaver and the second interleaver.

Moreover, in the Tanner graph chart of FIG. 74, v1 variable nodes withone branch connected with the first interleaver and no branch connectedwith the second interleaver exist, v2 variable nodes with one branchconnected with the first interleaver and two branches connected with thesecond interleaver exist, and v3 variable nodes with no branch connectedwith the first interleaver and two branches connected with the secondinterleaver exist, respectively.

Furthermore, in the Tanner graph chart of FIG. 74, c1 check nodes withtwo branches connected with the first interleaver and no branchconnected with the second interleaver exist, c2 check nodes with twobranches connected with the first interleaver and two branches connectedwith the second interleaver exist, and c3 check nodes with no branchconnected with the first interleaver and three branches connected withthe second interleaver exist, respectively.

Here, for example, the density evolution and the mounting thereof aredescribed in “On the Design of Low-Density Parity-Check Codes within0.0045 dB of the Shannon Limit”, S. Y. Chung, G. D. Forney, T. J.Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2,February 2001.

In simulation to find (a parity check matrix initial value table of) aSony code, by the density evaluation of the multi-edge type, an ensemblein which a performance threshold that is E_(b)/N₀ (signal-to-noise powerratio per bit) with deteriorating (decreasing) BER is equal to or lessthan a predetermined value is found, and an LDPC code that decreases BERin a case using one or more orthogonal modulations such as QPSK isselected from LDPC codes belonging to the ensemble as an LDPC code ofgood performance.

The parity check matrix initial value table of the Sony code is foundfrom the above-mentioned simulation.

Thus, according to the Sony symbol obtained from the parity check matrixinitial value table, it is possible to secure the excellentcommunication quality in the data transmission.

FIG. 75 is an illustration of parity check matrices H (hereinafter, alsoreferred to as “parity check matrices H of Sony symbols (16k, 8/15),(16k, 10/15), and (16k, 12/15)”) obtained from the parity check matrixinitial value table of the Sony symbols (16k, 8/15), (16k, 10/15), and(16k, 12/15).

Every minimum cycle length of the parity check matrices H of the Sonysymbols (16k, 8/15), (16k, 10/15), and (16k, 12/15) has a valueexceeding cycle 4, and thus there is no cycle 4 (a loop of 1 elements inwhich a loop length is 4). Here, the minimum cycle length (girth) is aminimum value of a length (a loop length) of a loop configured with 1elements in the parity check matrix H.

A performance threshold value of the Sony symbol (16k, 8/15) is set to0.805765, a performance threshold value of the Sony symbol (16k, 10/15)is set to 2.471011, and a performance threshold value of the Sony symbol(16k, 12/15) is set to 4.269922.

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the Sony symbols (16k, 8/15), (16k, 10/15), and (16k,12/15) starting from the 1st column, the column weight is set to X2 forKX2 columns subsequent thereto, the column weight is set to Y1 for KY1columns subsequent thereto, the column weight is set to Y2 for KY2columns subsequent thereto, the column weight is set to 2 for M−1columns subsequent thereto, and the column weight is set to 1 for thelast column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=16200 bits)of the Sony symbols (16k, 8/15), (16k, 10/15), and (16k, 12/15).

In the parity check matrices H of the Sony symbols (16k, 8/15), (16k,10/15), and (16k, 12/15), the numbers KX1, KX2, KY1, KY2, and M ofcolumns and column weights X1, X2, Y1, and Y2 are set as illustrated inFIG. 75.

In the parity check matrices H of the Sony symbols (16k, 8/15), (16k,10/15), and (16k, 12/15), similarly to the parity check matrix describedabove with reference to FIGS. 12 and 13, columns closer to the head side(the left side) have higher column weights, and thus a code bit at thehead of the Sony symbol tends to be robust to error (have errortolerance).

According to the simulation conducted by the applicant of the presentapplication, an excellent BER/FER is obtained for the Sony symbols (16k,8/15), (16k, 10/15), and (16k, 12/15), and thus it is possible to securethe excellent communication quality in the data transmission using theSony symbols (16k, 8/15), (16k, 10/15), and (16k, 12/15).

FIG. 76 is an illustration of parity check matrices H of the Sonysymbols (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15).

Every minimum cycle length of the parity check matrices H of the Sonysymbols (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15) has avalue exceeding a cycle 4, and thus there is no cycle 4.

A performance threshold value of the Sony symbol (64k, 7/15) is set to−0.093751, a performance threshold value of the Sony symbol (64k, 9/15)is set to 1.658523, a performance threshold value of the Sony symbol(64k, 11/15) is set to 3.351930, and a performance threshold value ofthe Sony symbol (64k, 13/15) is set to 5.301749.

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the Sony symbols (64k, 7/15), (64k, 9/15), (64k, 11/15),and (64k, 13/15) starting from the 1st column, the column weight is setto X2 for KX2 columns subsequent thereto, the column weight is set to Y1for KY1 columns subsequent thereto, the column weight is set to Y2 forKY2 columns subsequent thereto, the column weight is set to 2 for M−1columns subsequent thereto, and the column weight is set to 1 for thelast column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits)of the Sony symbols (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k,13/15).

In the parity check matrices H of the Sony symbols (64k, 7/15), (64k,9/15), (64k, 11/15), and (64k, 13/15), the numbers KX1, KX2, KY1, KY2,and M of columns and column weights X1, X2, Y1, and Y2 are set asillustrated in FIG. 76.

In the parity check matrices H of the Sony symbols (64k, 7/15), (64k,9/15), (64k, 11/15), and (64k, 13/15), similarly to the parity checkmatrix described above with reference to FIGS. 12 and 13, columns closerto the head side (the left side) have higher column weights, and thus acode bit at the head of the Sony symbol tends to be robust to error(have error tolerance).

According to the simulation conducted by the applicant of the presentapplication, an excellent BER/FER is obtained for the Sony symbols (64k,7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15), and thus it ispossible to secure the excellent communication quality in the datatransmission using the Sony symbols (64k, 7/15), (64k, 9/15), (64k,11/15), and (64k, 13/15).

FIG. 77 is an illustration of parity check matrices H of Samsung symbols(64k, 6/15), (64k, 8/15), and (64k, 12/15).

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the Samsung symbols (64k, 6/15), (64k, 8/15), and (64k,12/15) starting from the 1st column, the column weight is set to X2 forKX2 columns subsequent thereto, the column weight is set to Y1 for KY1columns subsequent thereto, the column weight is set to Y2 for KY2columns subsequent thereto, the column weight is set to 2 for M−1columns subsequent thereto, and the column weight is set to 1 for thelast column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits)of the Samsung symbols (64k, 6/15), (64k, 8/15), and (64k, 12/15).

In the parity check matrices H of the Samsung symbols (64k, 6/15), (64k,8/15), and (64k, 12/15), the numbers KX1, KX2, KY1, KY2, and M ofcolumns and column weights X1, X2, Y1, and Y2 are set as illustrated inFIG. 77.

FIG. 78 is an illustration of parity check matrices H of the LGE symbols(16k, 6/15), (16k, 7/15), (16k, 9/15), (16k, 11/15), and (16k, 13/15).

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the LGE symbols (16k, 6/15), (16k, 7/15), (16k, 9/15),(16k, 11/15), and (16k, 13/15) starting from the 1st column, the columnweight is set to X2 for KX2 columns subsequent thereto, the columnweight is set to Y1 for KY1 columns subsequent thereto, the columnweight is set to Y2 for KY2 columns subsequent thereto, the columnweight is set to 2 for M−1 columns subsequent thereto, and the columnweight is set to 1 for the last column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=16200 bits)of the LGE symbols (16k, 6/15), (16k, 7/15), (16k, 9/15), (16k, 11/15),and (16k, 13/15).

In the parity check matrices H of the LGE symbols (16k, 6/15), (16k,7/15), (16k, 9/15), (16k, 11/15), and (16k, 13/15), the numbers KX1,KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2are set as illustrated in FIG. 78.

FIG. 79 is an illustration of parity check matrices H of the LGE symbols(64k, 10/15).

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the LGE symbols (64k, 10/15) starting from the 1st column,the column weight is set to X2 for KX2 columns subsequent thereto, thecolumn weight is set to Y1 for KY1 columns subsequent thereto, thecolumn weight is set to Y2 for KY2 columns subsequent thereto, thecolumn weight is set to 2 for M−1 columns subsequent thereto, and thecolumn weight is set to 1 for the last column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits)of the LGE symbols (64k, 10/15).

In the parity check matrices H of the LGE symbols (64k, 10/15), thenumbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2,Y1, and Y2 are set as illustrated in FIG. 79.

FIG. 80 is an illustration of parity check matrices H of the NERCsymbols (64k, 9/15).

The column weight is set to X1 for KX1 columns of the parity checkmatrices H of the NERC symbols (64k, 9/15) starting from the 1st column,the column weight is set to X2 for KX2 columns subsequent thereto, thecolumn weight is set to Y1 for KY1 columns subsequent thereto, thecolumn weight is set to Y2 for KY2 columns subsequent thereto, thecolumn weight is set to 2 for M−1 columns subsequent thereto, and thecolumn weight is set to 1 for the last column.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits)of the NERC symbols (64k, 9/15).

In the parity check matrices H of the NERC symbols (64k, 9/15), thenumbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2,Y1, and Y2 are set as illustrated in FIG. 80.

FIG. 81 is an illustration of a parity check matrix H of an ETRI symbol(16k, 5/15).

For the parity check matrix H of the ETRI symbol (16k, 5/15), theparameter g=M₁ is 720.

Further, for the ETRI symbol (16k, 5/15), since the code length N is16200 and the encoding rate r is 5/15, the information length K=N×r is16200×5/15=5400 and the parity length M=N−K is 16200−5400=10800.

Further, the parameter M₂=M-M₁=N−K−g is 10800−720=10080.

Thus, the parameter Q₁=M₁/P is 720/360=2, and the parameter Q₂=M₂/P is10080/360=28.

FIG. 82 is an illustration of parity check matrices H of ETRI symbols of(64k, 5/15), (64k, 6/15), and (64k, 7/15).

For the parity check matrices H of the ETRI symbols of (64k, 5/15),(64k, 6/15), and (64k, 7/15), the parameters g=M₁, M₂, Q₁, and Q₂ areset as illustrated in FIG. 82.

<Constellation>

FIGS. 83 to 104 are illustrations of examples of constellation typesemployed in the transmission system of FIG. 7.

In the transmission system of FIG. 7, for example, a constellation usedin MODCOD can be set to MODCOD serving as a combination of a modulationscheme and an LDPC code.

In other words, in the transmission system of FIG. 7, for example, theLDPC codes can be classified into 9 types of LDPC codes in which theencoding rate r is 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15,and 13/15 according to the encoding rate r (regardless of the codelength N), and a combination of the 9 types of LDPC codes (each of theLDPC codes in which the encoding rate r is 5/15, 6/15, 7/15, 8/15, 9/15,10/15, 11/15, 12,15, and 13/15) and each modulation scheme can beemployed as MODCOD.

Further, in the transmission system of FIG. 7, one or more ofconstellations can be set to MODCOD of 1 using the modulation scheme ofMODCOD.

The constellations include uniform constellations (UCs) in which anarrangement of signal points is uniform, and non uniform constellations(NUCs) in which an arrangement of signal points is not uniform.

Examples of NUCs include a constellation called a 1-dimensional M²-QAMnon-uniform constellation (1D NUC) and a constellation called a2-dimensional QQAM non-uniform constellation (2D NUC).

Commonly, the 1D NUC is better in the BER than the UC, and the 2D NUC isbetter in the BER than the 1D NUC.

A constellation in which the modulation scheme is QPSK is the UC. Forexample, the 2D NUC can be employed as the constellation in which themodulation scheme is 16QAM, 64QAM, 256QAM, or the like, and for example,the 1D NUC can be employed as the constellation in which the modulationscheme is 1024QAM, 4096QAM, or the like.

Hereinafter, a constellation of an NUC used in MODCOD in which themodulation scheme is a modulation scheme in which an m-bit symbol ismapped to any of 2^(m) signal points, and an encoding rate of an LDPC isr is also referred to as NUC_2^(m)_r.

For example, “NUC_16_6/15” indicates a constellation of an NUC used inMODCOD in which the modulation scheme is 16QAM (or the modulation schemein which a symbol is mapped to any of 16 signal points), and theencoding rate r of the LDPC code is 6/15.

In the transmission system of FIG. 7, when the modulation scheme isQPSK, the same constellation is used for each encoding rate r of theLDPC code.

Further, in the transmission system of FIG. 7, when the modulationscheme is 16QAM, 64QAM, or 256QAM, a different constellation of a 2D NUCis used according to each encoding rate r of the LDPC code.

Further, in the transmission system of FIG. 7, when the modulationscheme is 1024QAM or 4096QAM, a different constellation of a 1D NUC isused according to each encoding rate r of the LDPC code.

Thus, as described above, when the LDPC codes are classified into the 9types of LDPC codes of r=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, 13/15 according to the encoding rate r, one type of constellation isprepared for QPSK, 9 types of constellations of a 2D NUC are preparedfor each of 16QAM, 64QAM, and 256QAM, and 9 types of constellations of a1D NUC are prepared for each of 1024QAM and 4096QAM.

FIG. 83 is an illustration of an example of a constellation of a 2D NUCfor each of 9 types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15,10/15, 11/15, 12,15, and 13/15) of LDPC codes when the modulation schemeis 16QAM.

FIG. 84 is an illustration of an example of a constellation of a 2D NUCfor each of 9 types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15,10/15, 11/15, 12,15, and 13/15) of LDPC codes when the modulation schemeis 64QAM.

FIG. 85 is an illustration of an example of a constellation of a 2D NUCfor each of 9 types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15,10/15, 11/15, 12,15, and 13/15) of LDPC codes when the modulation schemeis 256QAM.

FIG. 86 is an illustration of an example of a constellation of a 1D NUCfor each of 9 types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15,10/15, 11/15, 12,15, and 13/15) of LDPC codes when the modulation schemeis 1024QAM.

FIG. 87 and FIG. 88 are illustrations of examples of a constellation ofa 1D NUC for each of 9 types of encoding rates r (=5/15, 6/15, 7/15,8/15, 9/15, 10/15, 11/15, 12,15, and 13/15) of LDPC codes when themodulation scheme is 4096QAM.

In FIGS. 83 to 88, a horizontal axis and a vertical axis are an I axisand a Q axis, and Re{x₁} and Im{x₁} indicate a real part and animaginary part of a signal point x₁ serving as coordinates of the signalpoint x₁.

In FIGS. 83 to 88, a numerical value written after “for CR” indicatesthe encoding rate r of the LDPC code.

FIG. 89 is an illustration of an example of coordinates of a signalpoint of a UC that is used in common to 9 types of encoding rates r(=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, and 13/15) of LDPCcodes when the modulation scheme is QPSK.

In FIG. 89, “Input cell word y” indicates a 2-bit symbol that is mappedto a UC of QPSK, and “Constellation point z_(q)” indicates coordinates asignal point z_(q). An index q of the signal point z_(q) indicates adiscrete time (a time interval between a certain symbol and a nextsymbol) of a symbol.

In FIG. 89, coordinates of the signal point z_(q) are indicated in theform of a complex number, in which i indicates an imaginary unit(√(−1)).

FIG. 90 is an illustration of an example of coordinates of the signalpoint of the 2D NUC of FIG. 83 used for the 9 types of encoding rates r(=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, and 13/15) of theLDPC codes when the modulation scheme is 16QAM.

FIG. 91 is an illustration of an example of coordinates of the signalpoint of the 2D NUC of FIG. 84 used for the 9 types of encoding rates r(=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, and 13/15) of theLDPC codes when the modulation scheme is 64QAM.

FIGS. 92 and 93 are illustrations of an example of coordinates of thesignal point of the 2D NUC of FIG. 85 used for the 9 types of encodingrates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,15, and 13/15)of the LDPC codes when the modulation scheme is 256QAM.

In FIGS. 90 to 93, NUC_2^(m)_r indicates coordinates of a signal pointof a 2D NUC used when the modulation scheme is 2^(m)QAM, and theencoding rate of the LDPC code is r.

In FIGS. 90 to 93, similarly to FIG. 89, coordinates of the signal pointz_(q) are indicated in the form of a complex number, in which iindicates an imaginary unit.

In FIGS. 90 to 93, w#k indicates coordinates of a signal point of afirst quadrant of the constellation.

In the 2D NUC, a signal point of a second quadrant of the constellationis arranged at a position to which the signal point of the firstquadrant has moved symmetrically to the Q axis, and a signal point of athird quadrant of the constellation is arranged at a position to whichthe signal point of the first quadrant has moved symmetrically to anorigin. Further, a signal point of a fourth quadrant of theconstellation is arranged at a position to which the signal point of thefirst quadrant has moved symmetrically to the I axis.

Here, when the modulation scheme is 2^(m)QAM, m bits are used as onesymbol, and one symbol is mapped to a signal point corresponding to thesymbol.

The m-bit symbol is expressed by, for example, an integer value of 0 to2^(m)−1, but if b=2^(m)/4 is assumed, symbols y(0), y(1), . . . , andy(2^(m)−1) expressed by the integer value of 0 to 2^(m)−1 can beclassified into four symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) toy(3b−1), and y(3b) to y(4b−1).

In FIGS. 90 to 93, a suffix k of w#k has an integer value within a rangeof 0 to b−1, and w#k indicates coordinates of a signal pointcorresponding to the symbol y(k) within the range of the symbols y(0) toy(b−1).

Further, coordinates of a signal point corresponding to the symboly(k+b) within the range of the symbols y(b) to y(2b−1) are indicated by−conj(w#k), and coordinates of a signal point corresponding to thesymbol y(k+2b) within the range of the symbols y(2b) to y(3b−1) areindicated by conj(w#k). Further, coordinates of a signal pointcorresponding to the symbol y(k+3b) within the range of the symbolsy(3b) to y(4b−1) are indicated by −w#k.

Here, conj(w#k) indicates a complex conjugate of w#k.

For example, when the modulation scheme is 16QAM, the symbols y(0),y(1), . . . , and y(15) of m=4 bits are classified into four symbolsy(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15) ifb=2⁴/4=4.

Among the symbols y(0) to y(15), for example, the symbol y(12) is thesymbol y(k+3b)=y(0+3×4) within the symbols y(3b) to y(4b−1), and k iszero (0), and thus the coordinates of the signal point corresponding tothe symbol y(12) are −w#k=−w0.

Now, for example, if the encoding rate r of the LDPC code is 9/15,according to FIG. 90, when the modulation scheme is 16QAM, and theencoding rate r is 9/15, w0 of (NUC_16_9/15) is 0.4967+1.1932i, and thusthe coordinates −w0 of the signal point corresponding to the symboly(12) are −(0.4967+1.1932i).

FIG. 94 is an illustration of an example of the coordinates of thesignal point of the 1D NUC of FIG. 86 used for the 9 types of encodingrates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15)of the LDPC codes when the modulation scheme is 1024QAM.

In FIG. 94, a column of NUC_1k_r indicates a value of u#k indicating thecoordinates of the signal point of the 1D NUC used when the modulationscheme is 1024QAM, and the encoding rate of the LDPC code is r.

u#k indicates the real part Re(z_(q)) and the imaginary part Im(z_(q))of the complex number serving as the coordinates of the signal pointz_(q) of the 1D NUC.

FIG. 95 is an illustration of a relation between the symbol y of 1024QAMand u#k serving as each of the real part Re(z_(q)) and the imaginarypart Im(z_(q)) of the complex number indicating the coordinates of thesignal point z_(q) of the 1D NUC corresponding to the symbol y.

Now, the 10-bit symbol y of 1024QAM is assumed to be indicated byy_(0,q), y_(1,q), y_(2,q), y_(3,q), y_(4,q), y_(5,q), y_(6,q), y_(7,q),y_(8,q), and y_(9,q) from the first bit (the most significant bit).

A of FIG. 95 illustrates a correspondence relation between 5odd-numbered bits y_(0,q), y_(2,q), y_(4,q), y_(6,q), y_(8,q) of thesymbol y and u#k indicating the real part Re(z_(q)) (of the coordinates)of the signal point z_(q) corresponding to the symbol y.

B of FIG. 95 is a correspondence relation between 5 even-numbered bitsy_(1,q), y_(3,q), y_(5,q), y_(7,q), and y_(9,q) of the symbol y and u#kindicating the imaginary part Im(z_(q)) (of the coordinates) of thesignal point z_(q) corresponding to the symbol y.

For example, when the 10-bit symbol y=(y_(0,q), y_(1,q), y_(2,q),y_(3,q), y_(4,q), y_(5,q), y_(6,q), y_(7,q), y_(8,q), y_(9,q)) of1024QAM is (0, 0, 1, 0, 0, 1, 1, 1, 0, 0), the 5 odd-numbered bits(y_(0,q), y_(2,q), y_(4,q), y_(6,q), y_(8,q)) are (0, 1, 0, 1, 0), andthe 5 even-numbered bits (y_(1,q), y_(3,q), y_(5,q), y_(7,q), andy_(9,q)) are (0, 0, 1, 1, 0).

In A of FIG. 95, the 5 odd-numbered bits (0, 1, 0, 1, 0) are associatedwith u3, and thus the real part Re(z_(q)) of the signal point z_(q)corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3.

In B of FIG. 95, the 5 even-numbered bits (0, 0, 1, 1, 0) are associatedwith u11, and thus the imaginary part Im(z_(q)) of the signal pointz_(q) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0) isu11.

Meanwhile, for example, if the encoding rate r of the LDPC code is 7/15,according to FIG. 94, for the 1D NUC (NUC_1k_7/15) used when themodulation scheme is 1024QAM and the encoding rate r of the LDPC code is7/15, u3 is 1.1963, and u11 is 6.9391.

Thus, the real part Re(z_(q)) of the signal point z_(q) corresponding tothe symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3 (=1.1963), andIm(z_(q)) is u11 (=6.9391). As a result, the coordinates of the signalpoint z_(q) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0)are indicated by 1.1963+6.9391i.

FIG. 96 is an illustration of an example of the coordinates of thesignal point of the 1D NUC of FIGS. 87 and 88 used for the 9 types ofencoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15,and 13/15) of the LDPC codes when the modulation scheme is 4096QAM.

In FIG. 96, each column indicates a value of u#k indicating thecoordinates of the signal point of the 1D NUC used when the modulationscheme is 4096QAM and the encoding rates r of the LDPC codes are 5/15,6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15.

u#k indicates the real part Re(z_(q)) and the imaginary part Im(z_(q))of the complex number serving as the coordinates of the signal pointz_(q) of the 1D NUC.

FIG. 97 is an illustration of a relation between the symbol y of 4096QAMand u#k serving as each of the real part Re(z_(q)) and the imaginarypart Im(z_(q)) of the complex number indicating the coordinates of thesignal point z_(q) of the 1D NUC corresponding to the symbol y.

A method of obtaining the coordinates of the signal point of the 1D NUCof 4096QAM using FIGS. 96 and 97 is the same as the method of obtainingthe coordinates of the signal point of the 1D NUC of 1024QAM using FIGS.94 and 95, and thus a description thereof is omitted.

FIG. 98 is an illustration of another example of the constellation ofthe 2D NUC for each of the 9 types of encoding rates r of the LDPC codeswhen the modulation scheme is 16QAM.

FIG. 99 is an illustration of another example of the constellation ofthe 2D NUC for each of the 9 types of encoding rates r of the LDPC codeswhen the modulation scheme is 64QAM.

FIG. 100 is an illustration of another example of the constellation ofthe 2D NUC for each of the 9 types of encoding rates r of the LDPC codeswhen the modulation scheme is 256QAM.

In FIGS. 98 to 100, similarly to FIGS. 83 to 88, a horizontal axis and avertical axis are the I axis and the Q axis, and Re{x_(i)} and Im{x_(i)}indicate the real part and the imaginary part of the signal point x₁serving as the coordinates of the signal point x_(l). Further, in FIGS.98 to 100, a numerical value written after “for CR” indicates theencoding rate r of the LDPC code.

FIG. 101 is an illustration of another example of the coordinates of thesignal point of the 2D NUC of FIG. 98 used for each of the 9 types ofencoding rates r of the LDPC codes when the modulation scheme is 16QAM.

FIG. 102 is an illustration of another example of the coordinates of thesignal point of the 2D NUC of FIG. 99 used for each of the 9 types ofencoding rates r of the LDPC codes when the modulation scheme is 64QAM.

FIGS. 103 and 104 are illustrations of another example of thecoordinates of the signal point of the 2D NUC of FIG. 100 used for eachof the 9 types of encoding rates r of the LDPC codes when the modulationscheme is 256QAM.

In FIGS. 101 to 104, NUC_2^(m)_r indicates the coordinates of the signalpoint of the 2D NUC used when the modulation scheme is 2^(m)QAM, and theencoding rate of the LDPC code is r, similarly to FIGS. 90 to 93.

The signal points of the 1D NUC are arranged in a grid form on astraight line parallel to the I axis or a straight line parallel to theQ axis. However, an interval between the signal points is not constant.Further, when the signal point (the mapped data) is transmitted, averagepower of the signal points on the constellation is normalized. Thenormalization is performed by multiplying each signal point z_(q) on theconstellation by a reciprocal 1/(√P_(ave)) of a square root V/P_(ave) ofa root mean square value P_(ave) when a root mean square value of anabsolute value for (coordinates of) all signal points on theconstellation is indicated by P_(ave).

According to the constellations described above with reference to FIGS.83 to 104, it is confirmed that the excellent error rate is obtained.

<Block Interleaver 25>

FIG. 105 is a block diagram illustrating a configuration example of theblock interleaver 25 of FIG. 9.

The block interleaver 25 includes a storage region called a part 1 and astorage region called a part 2.

Each of the parts 1 and 2 is configured such that a number C of columnsequal in number to the number m of bits of the symbol and serving asstorage regions that store one bit in the row (horizontal) direction andstore a predetermined number of bits in the column (vertical) directionare arranged.

If the number of bits (hereinafter, also referred to as a part columnlength) that are stored in the column direction by the column of thepart 1 is indicated by R1, and the part column length of the column ofthe part 2 is indicated by R2, (R1+R2)×C is equal to the code length N(64800 bits or 16200 bits in the present embodiment) of the LDPC code ofthe block interleave target.

Further, the part column length R1 is equal to a multiple of 360 bitsserving as the unit size P, and the part column length R2 is equal to aremainder when a sum (hereinafter, also referred to as a column length)R1+R2 of the part column length R1 of the part 1 and the part columnlength R2 of the part 2 is divided by 360 bits serving as the unit sizeP.

Here, the column length R1+R2 is equal to a value obtained by dividingthe code length N of the LDPC code of the block interleave target by thenumber m of bits of the symbol.

For example, when 16QAM is employed as the modulation scheme for theLDPC code in which the code length N is 16200 bits, the number m of bitsof the symbol is 4 bits, and thus the column length R1+R2 is 4050(=16200/4) bits.

Further, since the remainder when the column length R1+R2=4050 isdivided by 360 bits serving as the unit size P is 90, the part columnlength R2 of the part 2 is 90 bits.

Further, the part column length R1 of the part 1 isR1+R2-R2=4050-90=3960 bits.

FIG. 106 is an illustration of the number C of columns of the parts 1and 2 and the part column lengths (the number of rows) R1 and R2 for acombination of the code length N and the modulation scheme.

FIG. 106 illustrates the number C of columns of the parts 1 and 2 andthe part column lengths R1 and R2 for combinations of the LDPC code inwhich the code length N is 16200 bits and the LDPC code in which thecode length N is 64800 bits and the modulation schemes of QPSK, 16QAM,64QAM, 256QAM, 1024QAM, and 4096QAM.

FIG. 107 is an illustration of the block interleave performed by theblock interleaver 25 of FIG. 105.

The block interleaver 25 performs the block interleave by writing theLDPC code in the parts 1 and 2 and reading the LDPC code from the parts1 and 2.

In other words, in the block interleave, writing of the code bits of theLDPC code of one code word downward (in the column direction) in thecolumn of the part 1 is performed from the column at the left side tothe column at the right side as illustrated in A of FIG. 107.

Then, when the writing of the code bits is completed to the bottom ofthe rightmost column (a C-th column) of the columns of the part 1,writing of the remaining code bits downward (in the column direction) inthe column of the part 2 is performed from the column at the left sideto the column at the right side.

Thereafter, when the writing of the code bits is completed to the bottomof the rightmost column (the C-th column) of the columns of the part 2,the code bits are read from the 1st rows of all the C columns of thepart 1 in the row direction in units of C=m bits.

Then, the reading of the code bits from all the C columns of the part 1is sequentially performed toward a row therebelow, and when the readingis completed up to an R1-th row serving as the last row, the code bitsare read from the 1st rows of all the C columns of the part 2 in the rowdirection in units of C=m bits.

The reading of the code bits from all the C columns of the part 2 issequentially performed toward a row therebelow and the reading isperformed up to an R2 row serving as the last row.

As a result, the code bits read from the parts 1 and 2 in units of mbits are supplied to the mapper 117 (FIG. 8) as the symbol.

<Group-Wise Interleave>

FIG. 108 is an illustration of the group-wise interleave performed bythe group-wise interleaver 24 of FIG. 9.

In the group-wise interleave, 360 bits of one segment are used as thebit group, where the LDPC code of one code word is divided into segmentsin units of 360 bits equal to the unit size P, and the LDPC code of onecode word is interleaved according to a predetermined pattern(hereinafter, also referred to as a GW pattern), starting from the head.

Here, when the LDPC code of one code word is segmented into the bitgroups, an (i+1)-th bit group from the head is also referred to as a bitgroup i.

When the unit size P is 360, for example, the LDPC code in which thecode length N is 1800 bits is segmented into bit groups 0, 1, 2, 3, and4, that is, 5 (=1800/360) bit groups. Further, for example, the LDPCcode in which the code length N is 16200 bits is segmented into bitgroups 0, 1, . . . , and 44, that is, 45 (=16200/360) bit groups, andthe LDPC code in which the code length N is 64800 bits is segmented intobit groups 0, 1, . . . , and 179, that is, 180 (=64800/360) bit groups.

Hereinafter, the GW pattern is assumed to be indicated by a sequence ofnumbers indicating a bit group. For example, for the LDPC code in whichthe code length N is 1800 bits, for example, the GW pattern 4, 2, 0, 3,1 indicates that a sequence of bit groups 0, 1, 2, 3, and 4 isinterleaved (rearranged) into a sequence of bit groups 4, 2, 0, 3, and1.

The GW pattern can be set at least for each code length N of the LDPCcode.

<Example of GW Pattern for LDPC Code of 64 Kbits>

FIG. 109 is an illustration of a 1st example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 109, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133,69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14,125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156,55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107,18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166,105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120,168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37,70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12,170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164,119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87,144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16,and 88.

FIG. 110 is an illustration of a 2nd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 110, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8,110, 7,78,94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92,151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146,179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48,74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99,173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12,64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36,106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153,141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137,76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125,96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and165.

FIG. 111 is an illustration of a 3rd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 111, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178,6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171,105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157,93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117,67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133,60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21,109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5,76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80,50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172,48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111,128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and20.

FIG. 112 is an illustration of a 4th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 112, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

139, 106, 125, 81, 88, 104, 3, 66, 60, 65, 2, 95, 155, 24, 151, 5, 51,53, 29, 75, 52, 85, 8, 22, 98, 93, 168, 15, 86, 126, 173, 100, 130, 176,20, 10, 87, 92, 175, 36, 143, 110, 67, 146, 149, 127, 133, 42, 84, 64,78, 1, 48, 159, 79, 138, 46, 112, 164, 31, 152, 57, 144, 69, 27, 136,122, 170, 132, 171, 129, 115, 107, 134, 89, 157, 113, 119, 135, 45, 148,83, 114, 71, 128, 161, 140, 26, 13, 59, 38, 35, 96, 28, 0, 80, 174, 137,49, 16, 101, 74, 179, 91, 44, 55, 169, 131, 163, 123, 145, 162, 108,178, 12, 77, 167, 21, 154, 82, 54, 90, 177, 17, 41, 39, 7, 102, 156, 62,109, 14, 37, 23, 153, 6, 147, 50, 47, 63, 18, 70, 68, 124, 72, 33, 158,32, 118, 99, 105, 94, 25, 121, 166, 120, 160, 141, 165, 111, 19, 150,97, 76, 73, 142, 117, 4, 172, 58, 11, 30, 9, 103, 40, 61, 43, 34, 56,and 116.

FIG. 113 is an illustration of a 5th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 113, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

72, 59, 65, 61, 80, 2, 66, 23, 69, 101, 19, 16, 53, 109, 74, 106, 113,56, 97, 30, 164, 15, 25, 20, 117, 76, 50, 82, 178, 13, 169, 36, 107, 40,122, 138, 42, 96, 27, 163, 46, 64, 124, 57, 87, 120, 168, 166, 39, 177,22, 67, 134, 9, 102, 28, 148, 91, 83, 88, 167, 32, 99, 140, 60, 152, 1,123, 29, 154, 26, 70, 149, 171, 12, 6, 55, 100, 62, 86, 114, 174, 132,139, 7, 45, 103, 130, 31, 49, 151, 119, 79, 41, 118, 126, 3, 179, 110,111, 51, 93, 145, 73, 133, 54, 104, 161, 37, 129, 63, 38, 95, 159, 89,112, 115, 136, 33, 68, 17, 35, 137, 173, 143, 78, 77, 141, 150, 58, 158,125, 156, 24, 105, 98, 43, 84, 92, 128, 165, 153, 108, 0, 121, 170, 131,144, 47, 157, 11, 155, 176, 48, 135, 4, 116, 146, 127, 52, 162, 142, 8,5, 34, 85, 90, 44, 172, 94, 160, 175, 75, 71, 18, 147, 10, 21, 14, and81.

FIG. 114 is an illustration of a 6th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 114, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

8, 27, 7, 70, 75, 84, 50, 131, 146, 99, 96, 141, 155, 157, 82, 57, 120,38, 137, 13, 83, 23, 40, 9, 56, 171, 124, 172, 39, 142, 20, 128, 133, 2,89, 153, 103, 112, 129, 151, 162, 106, 14, 62, 107, 110, 73, 71, 177,154, 80, 176, 24, 91, 32, 173, 25, 16, 17, 159, 21, 92, 6, 67, 81, 37,15, 136, 100, 64, 102, 163, 168, 18, 78, 76, 45, 140, 123, 118, 58, 122,11, 19, 86, 98, 119, 111, 26, 138, 125, 74, 97, 63, 10, 152, 161, 175,87, 52, 60, 22, 79, 104, 30, 158, 54, 145, 49, 34, 166, 109, 179, 174,93, 41, 116, 48, 3, 29, 134, 167, 105, 132, 114, 169, 147, 144, 77, 61,170, 90, 178, 0, 43, 149, 130, 117, 47, 44, 36, 115, 88, 101, 148, 69,46, 94, 143, 164, 139, 126, 160, 156, 33, 113, 65, 121, 53, 42, 66, 165,85, 127, 135, 5, 55, 150, 72, 35, 31, 51, 4, 1, 68, 12, 28, 95, 59, and108.

FIG. 115 is an illustration of a 7th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 115, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36,38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72,74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106,108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134,136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162,164, 166, 168, 170, 172, 174, 176, 178, 1, 3, 5, 7, 9, 11, 13, 15, 17,19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53,55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89,91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119,121, 123, 125, 127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147,149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175,177, and 179.

FIG. 116 is an illustration of an 8th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 116, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

11, 5, 8, 18, 1, 25, 32, 31, 19, 21, 50, 102, 65, 85, 45, 86, 98, 104,64, 78, 72, 53, 103, 79, 93, 41, 82, 108, 112, 116, 120, 124, 128, 132,136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 4, 12, 15, 3, 10,20, 26, 34, 23, 33, 68, 63, 69, 92, 44, 90, 75, 56, 100, 47, 106, 42,39, 97, 99, 89, 52, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145,149, 153, 157, 161, 165, 169, 173, 177, 6, 16, 14, 7, 13, 36, 28, 29,37, 73, 70, 54, 76, 91, 66, 80, 88, 51, 96, 81, 95, 38, 57, 105, 107,59, 61, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158,162, 166, 170, 174, 178, 0, 9, 17, 2, 27, 30, 24, 22, 35, 77, 74, 46,94, 62, 87, 83, 101, 49, 43, 84, 48, 60, 67, 71, 58, 40, 55, 111, 115,119, 123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,175, and 179.

FIG. 117 is an illustration of a 9th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 117, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

9, 18, 15, 13, 35, 26, 28, 99, 40, 68, 85, 58, 63, 104, 50, 52, 94, 69,108, 114, 120, 126, 132, 138, 144, 150, 156, 162, 168, 174, 8, 16, 17,24, 37, 23, 22, 103, 64, 43, 47, 56, 92, 59, 70, 42, 106, 60, 109, 115,121, 127, 133, 139, 145, 151, 157, 163, 169, 175, 4, 1, 10, 19, 30, 31,89, 86, 77, 81, 51, 79, 83, 48, 45, 62, 67, 65, 110, 116, 122, 128, 134,140, 146, 152, 158, 164, 170, 176, 6, 2, 0, 25, 20, 34, 98, 105, 82, 96,90, 107, 53, 74, 73, 93, 55, 102, 111, 117, 123, 129, 135, 141, 147,153, 159, 165, 171, 177, 14, 7, 3, 27, 21, 33, 44, 97, 38, 75, 72, 41,84, 80, 100, 87, 76, 57, 112, 118, 124, 130, 136, 142, 148, 154, 160,166, 172, 178, 5, 11, 12, 32, 29, 36, 88, 71, 78, 95, 49, 54, 61, 66,46, 39, 101, 91, 113, 119, 125, 131, 137, 143, 149, 155, 161, 167, 173,and 179.

FIG. 118 is an illustration of a 10th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 118, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

0, 14, 19, 21, 2, 11, 22, 9, 8, 7, 16, 3, 26, 24, 27, 80, 100, 121, 107,31, 36, 42, 46, 49, 75, 93, 127, 95, 119, 73, 61, 63, 117, 89, 99, 129,52, 111, 124, 48, 122, 82, 106, 91, 92, 71, 103, 102, 81, 113, 101, 97,33, 115, 59, 112, 90, 51, 126, 85, 123, 40, 83, 53, 69, 70, 132, 134,136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162,164, 166, 168, 170, 172, 174, 176, 178, 4, 5, 10, 12, 20, 6, 18, 13, 17,15, 1, 29, 28, 23, 25, 67, 116, 66, 104, 44, 50, 47, 84, 76, 65, 130,56, 128, 77, 39, 94, 87, 120, 62, 88, 74, 35, 110, 131, 98, 60, 37, 45,78, 125, 41, 34, 118, 38, 72, 108, 58, 43, 109, 57, 105, 68, 86, 79, 96,32, 114, 64, 55, 30, 54, 133, 135, 137, 139, 141, 143, 145, 147, 149,151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177,and 179.

FIG. 119 is an illustration of an 11th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 119, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

21, 11, 12, 9, 0, 6, 24, 25, 85, 103, 118, 122, 71, 101, 41, 93, 55, 73,100, 40, 106, 119, 45, 80, 128, 68, 129, 61, 124, 36, 126, 117, 114,132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 20, 18, 10,13, 16, 8, 26, 27, 54, 111, 52, 44, 87, 113, 115, 58, 116, 49, 77, 95,86, 30, 78, 81, 56, 125, 53, 89, 94, 50, 123, 65, 83, 133, 137, 141,145, 149, 153, 157, 161, 165, 169, 173, 177, 2, 17, 1, 4, 7, 15, 29, 82,32, 102, 76, 121, 92, 130, 127, 62, 107, 38, 46, 43, 110, 75, 104, 70,91, 69, 96, 120, 42, 34, 79, 35, 105, 134, 138, 142, 146, 150, 154, 158,162, 166, 170, 174, 178, 19, 5, 3, 14, 22, 28, 23, 109, 51, 108, 131,33, 84, 88, 64, 63, 59, 57, 97, 98, 48, 31, 99, 37, 72, 39, 74, 66, 60,67, 47, 112, 90, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175,and 179.

FIG. 120 is an illustration of a 12th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 120, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

12, 15, 2, 16, 27, 50, 35, 74, 38, 70, 108, 32, 112, 54, 30, 122, 72,116, 36, 90, 49, 85, 132, 138, 144, 150, 156, 162, 168, 174, 0, 14, 9,5, 23, 66, 68, 52, 96, 117, 84, 128, 100, 63, 60, 127, 81, 99, 53, 55,103, 95, 133, 139, 145, 151, 157, 163, 169, 175, 10, 22, 13, 11, 28,104, 37, 57, 115, 46, 65, 129, 107, 75, 119, 110, 31, 43, 97, 78, 125,58, 134, 140, 146, 152, 158, 164, 170, 176, 4, 19, 6, 8, 24, 44, 101,94, 118, 130, 69, 71, 83, 34, 86, 124, 48, 106, 89, 40, 102, 91, 135,141, 147, 153, 159, 165, 171, 177, 3, 20, 7, 17, 25, 87, 41, 120, 47,80, 59, 62, 88, 45, 56, 131, 61, 126, 113, 92, 51, 98, 136, 142, 148,154, 160, 166, 172, 178, 21, 18, 1, 26, 29, 39, 73, 121, 105, 77, 42,114, 93, 82, 111, 109, 67, 79, 123, 64, 76, 33, 137, 143, 149, 155, 161,167, 173, and 179.

FIG. 121 is an illustration of a 13th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 121, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36,38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72,74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106,108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134,136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162,164, 166, 168, 170, 172, 174, 176, 178, 1, 3, 5, 7, 9, 11, 13, 15, 17,19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53,55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89,91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119,121, 123, 125, 127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147,149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175,177, and 179.

FIG. 122 is an illustration of a 14th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 122, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72,76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132,136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 1, 5, 9, 13, 17,21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89,93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149,153, 157, 161, 165, 169, 173, 177, 2, 6, 10, 14, 18, 22, 26, 30, 34, 38,42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106,110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162,166, 170, 174, 178, 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,55, 59, 63, 67, 71, 75, 79, 83, 87, 91, 95, 99, 103, 107, 111, 115, 119,123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175,and 179.

FIG. 123 is an illustration of a 15th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 123, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

8, 112, 92, 165, 12, 55, 5, 126, 87, 70, 69, 94, 103, 78, 137, 148, 9,60, 13, 7, 178, 79, 43, 136, 34, 68, 118, 152, 49, 15, 99, 61, 66, 28,109, 125, 33, 167, 81, 93, 97, 26, 35, 30, 153, 131, 122, 71, 107, 130,76, 4, 95, 42, 58, 134, 0, 89, 75, 40, 129, 31, 80, 101, 52, 16, 142,44, 138, 46, 116, 27, 82, 88, 143, 128, 72, 29, 83, 117, 172, 14, 51,159, 48, 160, 100, 1, 102, 90, 22, 3, 114, 19, 108, 113, 39, 73, 111,155, 106, 105, 91, 150, 54, 25, 135, 139, 147, 36, 56, 123, 6, 67, 104,96, 157, 10, 62, 164, 86, 74, 133, 120, 174, 53, 140, 156, 171, 149,127, 85, 59, 124, 84, 11, 21, 132, 41, 145, 158, 32, 17, 23, 50, 169,170, 38, 18, 151, 24, 166, 175, 2, 47, 57, 98, 20, 177, 161, 154, 176,163, 37, 110, 168, 141, 64, 65, 173, 162, 121, 45, 77, 115, 179, 63,119, 146, and 144.

FIG. 124 is an illustration of a 16th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 124 a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

103, 138, 168, 82, 116, 45, 178, 28, 160, 2, 129, 148, 150, 23, 54, 106,24, 78, 49, 87, 145, 179, 26, 112, 119, 12, 18, 174, 21, 48, 134, 137,102, 147, 152, 72, 68, 3, 22, 169, 30, 64, 108, 142, 131, 13, 113, 115,121, 37, 133, 136, 101, 59, 73, 161, 38, 164, 43, 167, 42, 144, 41, 85,91, 58, 128, 154, 172, 57, 75, 17, 157, 19, 4, 86, 15, 25, 35, 9, 105,123, 14, 34, 56, 111, 60, 90, 74, 149, 146, 62, 163, 31, 16, 141, 88, 6,155, 130, 89, 107, 135, 79, 8, 10, 124, 171, 114, 162, 33, 66, 126, 71,44, 158, 51, 84, 165, 173, 120, 7, 11, 170, 176, 1, 156, 96, 175, 153,36, 47, 110, 63, 132, 29, 95, 143, 98, 70, 20, 122, 53, 100, 93, 140,109, 139, 76, 151, 52, 61, 46, 125, 94, 50, 67, 81, 69, 65, 40, 127, 77,32, 39, 27, 99, 97, 159, 166, 80, 117, 55, 92, 118, 0, 5, 83, 177, and104.

FIG. 125 is an illustration of a 17th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 125, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

104, 120, 47, 136, 116, 109, 22, 20, 117, 61, 52, 108, 86, 99, 76, 90,37, 58, 36, 138, 95, 130, 177, 93, 56, 33, 24, 82, 0, 67, 83, 46, 79,70, 154, 18, 75, 43, 49, 63, 162, 16, 167, 80, 125, 1, 123, 107, 9, 45,53, 15, 38, 23, 57, 141, 4, 178, 165, 113, 21, 105, 11, 124, 126, 77,146, 29, 131, 27, 176, 40, 74, 91, 140, 64, 73, 44, 129, 157, 172, 51,10, 128, 119, 163, 103, 28, 85, 156, 78, 6, 8, 173, 160, 106, 31, 54,122, 25, 139, 68, 150, 164, 87, 135, 97, 166, 42, 169, 161, 137, 26, 39,133, 5, 94, 69, 2, 30, 171, 149, 115, 96, 145, 101, 92, 143, 12, 88, 81,71, 19, 147, 50, 152, 159, 155, 151, 174, 60, 32, 3, 142, 72, 14, 170,112, 65, 89, 175, 158, 17, 114, 62, 144, 13, 98, 66, 59, 7, 118, 48,153, 100, 134, 84, 111, 132, 127, 41, 168, 110, 102, 34, 121, 179, 148,55, and 35.

FIG. 126 is an illustration of a 18th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 126, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

37, 98, 160, 63, 18, 6, 94, 136, 8, 50, 0, 75, 65, 32, 107, 60, 108, 17,21, 156, 157, 5, 73, 66, 38, 177, 162, 130, 171, 76, 57, 126, 103, 62,120, 134, 154, 101, 143, 29, 13, 149, 16, 33, 55, 56, 159, 128, 23, 146,153, 141, 169, 49, 46, 152, 89, 155, 111, 127, 48, 14, 93, 41, 7, 78,135, 69, 123, 179, 36, 87, 27, 58, 88, 170, 125, 110, 15, 97, 178, 90,121, 173, 30, 102, 10, 80, 104, 166, 64, 4, 147, 1, 52, 45, 148, 68,158, 31, 140, 100, 85, 115, 151, 70, 39, 82, 122, 79, 12, 91, 133, 132,22, 163, 47, 19, 119, 144, 35, 25, 42, 83, 92, 26, 72, 138, 54, 124, 24,74, 118, 117, 168, 71, 109, 112, 106, 176, 175, 44, 145, 11, 9, 161, 96,77, 174, 137, 34, 84, 2, 164, 129, 43, 150, 61, 53, 20, 165, 113, 142,116, 95, 3, 28, 40, 81, 99, 139, 114, 59, 67, 172, 131, 105, 167, 51,and 86.

FIG. 127 is an illustration of a 19th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 127, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

58, 70, 23, 32, 26, 63, 55, 48, 35, 41, 53, 20, 38, 51, 61, 65, 44, 29,7, 2, 113, 68, 96, 104, 106, 89, 27, 0, 119, 21, 4, 49, 46, 100, 13, 36,57, 98, 102, 9, 42, 39, 33, 62, 22, 95, 101, 15, 91, 25, 93, 132, 69,87, 47, 59, 67, 124, 17, 11, 31, 43, 40, 37, 85, 50, 97, 140, 45, 92,56, 30, 34, 60, 107, 24, 52, 94, 64, 5, 71, 90, 66, 103, 88, 86, 84, 19,169, 159, 147, 126, 28, 130, 14, 162, 144, 166, 108, 153, 115, 135, 120,122, 112, 139, 151, 156, 16, 172, 164, 123, 99, 54, 136, 81, 105, 128,116, 150, 155, 76, 18, 142, 170, 175, 83, 146, 78, 109, 73, 131, 127,82, 167, 77, 110, 79, 137, 152, 3, 173, 148, 72, 158, 117, 1, 6, 12, 8,161, 74, 143, 133, 168, 171, 134, 163, 138, 121, 141, 160, 111, 10, 149,80, 75, 165, 157, 174, 129, 145, 114, 125, 154, 118, 176, 177, 178, and179.

FIG. 128 is an illustration of a 20th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 128, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

40, 159, 100, 14, 88, 75, 53, 24, 157, 84, 23, 77, 140, 145, 32, 28,112, 39, 76, 50, 93, 27, 107, 25, 152, 101, 127, 5, 129, 71, 9, 21, 96,73, 35, 106, 158, 49, 136, 30, 137, 115, 139, 48, 167, 85, 74, 72, 7,110, 161, 41, 170, 147, 82, 128, 149, 33, 8, 120, 47, 68, 58, 67, 87,155, 11, 18, 103, 151, 29, 36, 83, 135, 79, 150, 97, 54, 70, 138, 156,31, 121, 34, 20, 130, 61, 57, 2, 166, 117, 15, 6, 165, 118, 98, 116,131, 109, 62, 126, 175, 22, 111, 164, 16, 133, 102, 55, 105, 64, 177,78, 37, 162, 124, 119, 19, 4, 69, 132, 65, 123, 160, 17, 52, 38, 1, 80,90, 42, 81, 104, 13, 144, 51, 114, 3, 43, 146, 163, 59, 45, 89, 122,169, 44, 94, 86, 99, 66, 171, 173, 0, 141, 148, 176, 26, 143, 178, 60,153, 142, 91, 179, 12, 168, 113, 95, 174, 56, 134, 92, 46, 108, 125, 10,172, 154, and 63.

FIG. 129 is an illustration of a 21st example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 129, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

143, 57, 67, 26, 134, 112, 136, 103, 13, 94, 16, 116, 169, 95, 98, 6,174, 173, 102, 15, 114, 39, 127, 78, 18, 123, 121, 4, 89, 115, 24, 108,74, 63, 175, 82, 48, 20, 104, 92, 27, 3, 33, 106, 62, 148, 154, 25, 129,69, 178, 156, 87, 83, 100, 122, 70, 93, 50, 140, 43, 125, 166, 41, 128,85, 157, 49, 86, 66, 79, 130, 133, 171, 21, 165, 126, 51, 153, 38, 142,109, 10, 65, 23, 91, 90, 73, 61, 42, 47, 131, 77, 9, 58, 96, 101, 37, 7,159, 44, 2, 170, 160, 162, 0, 137, 31, 45, 110, 144, 88, 8, 11, 40, 81,168, 135, 56, 151, 107, 105, 32, 120, 132, 1, 84, 161, 179, 72, 176, 71,145, 139, 75, 141, 97, 17, 149, 124, 80, 60, 36, 52, 164, 53, 158, 113,34, 76, 5, 111, 155, 138, 19, 35, 167, 172, 14, 147, 55, 152, 59, 64,54, 117, 146, 118, 119, 150, 29, 163, 68, 99, 46, 177, 28, 22, 30, and12.

FIG. 130 is an illustration of a 22nd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 130, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

116, 47, 155, 89, 109, 137, 103, 60, 114, 14, 148, 100, 28, 132, 129,105, 154, 7, 167, 140, 160, 30, 57, 32, 81, 3, 86, 45, 69, 147, 125, 52,20, 22, 156, 168, 17, 5, 93, 53, 61, 149, 56, 62, 112, 48, 11, 21, 166,73, 158, 104, 79, 128, 135, 126, 63, 26, 44, 97, 13, 151, 123, 41, 118,35, 131, 8, 90, 58, 134, 6, 78, 130, 82, 106, 99, 178, 102, 29, 108,120, 107, 139, 23, 85, 36, 172, 174, 138, 95, 145, 170, 122, 50, 19, 91,67, 101, 92, 179, 27, 94, 66, 171, 39, 68, 9, 59, 146, 15, 31, 38, 49,37, 64, 77, 152, 144, 72, 165, 163, 24, 1, 2, 111, 80, 124, 43, 136,127, 153, 75, 42, 113, 18, 164, 133, 142, 98, 96, 4, 51, 150, 46, 121,76, 10, 25, 176, 34, 110, 115, 143, 173, 169, 40, 65, 157, 175, 70, 33,141, 71, 119, 16, 162, 177, 12, 84, 87, 117, 0, 88, 161, 55, 54, 83, 74,and 159.

FIG. 131 is an illustration of a 23rd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 131, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

62, 17, 10, 25, 174, 13, 159, 14, 108, 0, 42, 57, 78, 67, 41, 132, 110,87, 77, 27, 88, 56, 8, 161, 7, 164, 171, 44, 75, 176, 145, 165, 157, 34,142, 98, 103, 52, 11, 82, 141, 116, 15, 158, 139, 120, 36, 61, 20, 112,144, 53, 128, 24, 96, 122, 114, 104, 150, 50, 51, 80, 109, 33, 5, 95,59, 16, 134, 105, 111, 21, 40, 146, 18, 133, 60, 23, 160, 106, 32, 79,55, 6, 1, 154, 117, 19, 152, 167, 166, 30, 35, 100, 74, 131, 99, 156,39, 76, 86, 43, 178, 155, 179, 177, 136, 175, 81, 64, 124, 153, 84, 163,135, 115, 125, 47, 45, 143, 72, 48, 172, 97, 85, 107, 126, 91, 129, 137,83, 118, 54, 2, 9, 58, 169, 73, 123, 4, 92, 168, 162, 94, 138, 119, 22,31, 63, 89, 90, 69, 49, 173, 28, 127, 26, 29, 101, 170, 93, 140, 147,149, 148, 66, 65, 121, 12, 71, 37, 70, 102, 46, 38, 68, 130, 3, 113, and151.

FIG. 132 is an illustration of a 24th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 132, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

168, 18, 46, 131, 88, 90, 11, 89, 111, 174, 172, 38, 78, 153, 9, 80, 53,27, 44, 79, 35, 83, 171, 51, 37, 99, 95, 119, 117, 127, 112, 166, 28,123, 33, 160, 29, 6, 135, 10, 66, 69, 74, 92, 15, 109, 106, 178, 65,141, 0, 3, 154, 156, 164, 7, 45, 115, 122, 148, 110, 24, 121, 126, 23,175, 21, 113, 58, 43, 26, 143, 56, 142, 39, 147, 30, 25, 101, 145, 136,19, 4, 48, 158, 118, 133, 49, 20, 102, 14, 151, 5, 2, 72, 103, 75, 60,84, 34, 157, 169, 31, 161, 81, 70, 85, 159, 132, 41, 152, 179, 98, 144,36, 16, 87, 40, 91, 1, 130, 108, 139, 94, 97, 8, 104, 13, 150, 137, 47,73, 62, 12, 50, 61, 105, 100, 86, 146, 165, 22, 17, 57, 167, 59, 96,120, 155, 77, 162, 55, 68, 140, 134, 82, 76, 125, 32, 176, 138, 173,177, 163, 107, 170, 71, 129, 63, 93, 42, 52, 116, 149, 54, 128, 124,114, 67, and 64.

FIG. 133 is an illustration of a 25th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 133, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

18, 150, 165, 42, 81, 48, 63, 45, 93, 152, 25, 16, 174, 29, 47, 83, 8,60, 30, 66, 11, 113, 44, 148, 4, 155, 59, 33, 134, 99, 32, 176, 109, 72,36, 111, 106, 73, 170, 126, 64, 88, 20, 17, 172, 154, 120, 121, 139, 77,98, 43, 105, 133, 19, 41, 78, 15, 7, 145, 94, 136, 131, 163, 65, 31, 96,79, 119, 143, 10, 95, 9, 146, 14, 118, 162, 37, 97, 49, 22, 51, 127, 6,71, 132, 87, 21, 39, 38, 54, 115, 159, 161, 84, 108, 13, 102, 135, 103,156, 67, 173, 76, 75, 164, 52, 142, 69, 130, 56, 153, 74, 166, 158, 124,141, 58, 116, 85, 175, 169, 168, 147, 35, 62, 5, 123, 100, 90, 122, 101,149, 112, 140, 86, 68, 89, 125, 27, 177, 160, 0, 80, 55, 151, 53, 2, 70,167, 114, 129, 179, 138, 1, 92, 26, 50, 28, 110, 61, 82, 91, 117, 107,178, 34, 157, 137, 128, 40, 24, 57, 3, 171, 46, 104, 12, 144, and 23.

FIG. 134 is an illustration of a 26th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 134, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

18, 8, 166, 117, 4, 111, 142, 148, 176, 91, 120, 144, 99, 124, 20, 25,31, 78, 36, 72, 2, 98, 93, 74, 174, 52, 152, 62, 88, 75, 23, 97, 147,15, 71, 1, 127, 138, 81, 83, 68, 94, 112, 119, 121, 89, 163, 85, 86, 28,17, 64, 14, 44, 158, 159, 150, 32, 128, 70, 90, 29, 30, 63, 100, 65,129, 140, 177, 46, 84, 92, 10, 33, 58, 7, 96, 151, 171, 40, 76, 6, 3,37, 104, 57, 135, 103, 141, 107, 116, 160, 41, 153, 175, 55, 130, 118,131, 42, 27, 133, 95, 179, 34, 21, 87, 106, 105, 108, 79, 134, 113, 26,164, 114, 73, 102, 77, 22, 110, 161, 43, 122, 123, 82, 5, 48, 139, 60,49, 154, 115, 146, 67, 69, 137, 109, 143, 24, 101, 45, 16, 12, 19, 178,80, 51, 47, 149, 50, 172, 170, 169, 61, 9, 39, 136, 59, 38, 54, 156,126, 125, 145, 0, 13, 155, 132, 162, 11, 157, 66, 165, 173, 56, 168,167, 53, and 35.

FIG. 135 is an illustration of a 27th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 135, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

77, 50, 109, 128, 153, 12, 48, 17, 147, 55, 173, 172, 135, 121, 99, 162,52, 40, 129, 168, 103, 87, 134, 105, 179, 10, 131, 151, 3, 26, 100, 15,123, 88, 18, 91, 54, 160, 49, 1, 76, 80, 74, 31, 47, 58, 161, 9, 16, 34,41, 21, 177, 11, 63, 6, 39, 165, 169, 125, 114, 57, 37, 67, 93, 96, 73,106, 83, 166, 24, 51, 142, 65, 43, 64, 53, 72, 156, 81, 4, 155, 33, 163,56, 150, 70, 167, 107, 112, 144, 149, 36, 32, 35, 59, 101, 29, 127, 138,176, 90, 141, 92, 170, 102, 119, 25, 75, 14, 0, 68, 20, 97, 110, 28, 89,118, 154, 126, 2, 22, 124, 85, 175, 78, 46, 152, 23, 86, 27, 79, 130,66, 45, 113, 111, 62, 61, 7, 30, 133, 108, 171, 143, 60, 178, 5, 122,44, 38, 148, 157, 84, 42, 139, 145, 8, 104, 115, 71, 137, 132, 146, 164,98, 13, 117, 174, 158, 95, 116, 140, 94, 136, 120, 82, 69, 159, and 19.

FIG. 136 is an illustration of a 28th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 136, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

51, 47, 53, 43, 55, 59, 49, 33, 35, 31, 24, 37, 0, 2, 45, 41, 39, 57,42, 44, 52, 40, 23, 30, 32, 34, 54, 56, 46, 50, 122, 48, 1, 36, 38, 58,77, 3, 65, 81, 67, 147, 83, 69, 26, 75, 85, 73, 79, 145, 71, 63, 5, 61,70, 78, 68, 62, 66, 6, 64, 149, 60, 82, 80, 4, 76, 84, 72, 154, 86, 74,89, 128, 137, 91, 141, 93, 101, 7, 87, 9, 103, 99, 95, 11, 13, 143, 97,133, 136, 12, 100, 94, 14, 88, 142, 96, 92, 8, 152, 10, 139, 102, 104,132, 90, 98, 114, 112, 146, 123, 110, 15, 125, 150, 120, 153, 29, 106,134, 27, 127, 108, 130, 116, 28, 107, 126, 25, 131, 124, 129, 151, 121,105, 111, 115, 135, 148, 109, 117, 158, 113, 170, 119, 162, 178, 155,176, 18, 20, 164, 157, 160, 22, 140, 16, 168, 166, 172, 174, 175, 179,118, 138, 156, 19, 169, 167, 163, 173, 161, 177, 165, 144, 171, 17, 21,and 159.

FIG. 137 is an illustration of a 29th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 137, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

49, 2, 57, 47, 31, 35, 24, 39, 59, 0, 45, 41, 55, 53, 51, 37, 33, 43,56, 38, 48, 32, 50, 23, 34, 54, 1, 36, 44, 52, 40, 58, 122, 46, 42, 30,3, 75, 73, 65, 145, 71, 79, 67, 69, 83, 85, 147, 63, 81, 77, 61, 5, 26,62, 64, 74, 70, 82, 149, 76, 4, 78, 84, 80, 86, 66, 68, 72, 6, 60, 154,103, 95, 101, 143, 9, 89, 141, 128, 97, 137, 133, 7, 13, 99, 91, 93, 87,11, 136, 90, 88, 94, 10, 8, 14, 96, 104, 92, 132, 142, 100, 98, 12, 102,152, 139, 150, 106, 146, 130, 27, 108, 153, 112, 114, 29, 110, 134, 116,15, 127, 125, 123, 120, 148, 151, 113, 126, 124, 135, 129, 109, 25, 28,158, 117, 105, 115, 111, 131, 107, 121, 18, 170, 164, 20, 140, 160, 166,162, 119, 155, 168, 178, 22, 174, 172, 176, 16, 157, 159, 171, 161, 118,17, 163, 21, 165, 19, 179, 177, 167, 138, 173, 156, 144, 169, and 175.

FIG. 138 is an illustration of a 30th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 138, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151, 66, 92,140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110, 128, 73, 148,14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122, 150, 103, 178,119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143, 147, 89, 4, 107,33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153, 90, 152, 124, 7, 30,31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175, 94, 115, 15, 112, 99, 13,21, 42, 169, 76, 19, 168, 16, 27, 162, 167, 164, 97, 82, 44, 106, 12,109, 132, 145, 161, 174, 95, 0, 105, 134, 173, 84, 9, 65, 88, 54, 67,116, 154, 80, 22, 172, 60, 111, 133, 56, 170, 104, 131, 123, 24, 49,113, 136, 55, 3, 157, 156, 35, 58, 45, 155, 70, 59, 57, 171, 176, 74,117, 18, 127, 114, 11, 69, 158, 129, 139, 62, 135, 96, 142, 41, 130,160, 2, 126, 51, and 137.

FIG. 139 is an illustration of a 31th example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 139, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26, 84, 123,89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25, 32, 62, 91, 4,20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2, 34, 43, 168, 14, 64,142, 115, 87, 38, 147, 39, 51, 152, 56, 86, 122, 76, 57, 129, 172, 6,126, 10, 97, 85, 164, 3, 80, 90, 79, 124, 138, 120, 17, 103, 99, 116,46, 98, 162, 151, 143, 11, 175, 160, 96, 132, 81, 171, 94, 65, 118, 161,125, 178, 95, 112, 88, 174, 13, 35, 1, 167, 0, 128, 12, 58, 29, 169, 67,28, 119, 166, 60, 55, 54, 130, 92, 146, 177, 149, 111, 9, 173, 179, 176,75, 77, 114, 48, 159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18,69, 109, 16, 121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53,140, 153, 158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40,155.

FIG. 140 is an illustration of a 32nd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 140, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139, 106, 69,49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47, 177, 6, 132,45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93, 89, 92, 135, 4, 71,87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18, 91, 118, 3, 82, 144,113, 121, 54, 84, 97, 122, 120, 7, 154, 56, 134, 57, 161, 33, 116, 28,96, 72, 172, 12, 115, 38, 164, 32, 167, 145, 17, 88, 39, 151, 80, 0,136, 169, 142, 74, 147, 126, 166, 163, 40, 110, 171, 50, 160, 131, 70,175, 103, 125, 77, 162, 31, 85, 66, 67, 52, 108, 159, 133, 42, 153, 21,51, 119, 123, 98, 35, 48, 111, 149, 25, 58, 60, 158, 102, 59, 117, 20,141, 143, 46, 53, 155, 15, 165, 152, 112, 176, 105, 178, 99, 174, 168,114, 179, 78, 10, 19, 62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55,137, 81, and 79.

FIG. 141 is an illustration of a 33rd example of the GW pattern for anLDPC code in which the code length N is 64 kbits.

According to the GW pattern of FIG. 141, a sequence of bit groups 0 to179 of the LDPC code of 64 kbits is interleaved into a sequence of bitgroups

98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142, 176, 95, 71,19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35, 76, 80, 140, 77,10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83, 137, 41, 109, 2, 66,133, 62, 135, 28, 93, 128, 86, 57, 153, 161, 110, 52, 147, 141, 31, 79,32, 88, 160, 84, 150, 6, 100, 73, 126, 164, 17, 42, 101, 7, 55, 105, 91,22, 130, 154, 1, 82, 14, 0, 9, 21, 50, 165, 72, 138, 175, 106, 108, 3,169, 30, 157, 54, 18, 20, 44, 34, 134, 107, 56, 53, 15, 162, 38, 166,24, 33, 60, 85, 145, 115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146,90, 129, 119, 111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68,177, 94, 179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127,174, 74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,and 123.

The 1st to 33rd examples of the GW pattern for the LDPC code in whichthe code length N is 64 kbits can be applied to any combination of theLDPC code in which the code length N is 64 kbits with an arbitraryencoding rate r and modulation scheme (constellation).

However, when the GW pattern to be applied to the group-wise interleaveis set for each combination of the code length N of the LDPC code, theencoding rate r of the LDPC code, and the modulation scheme(constellation), the error rate of each combination can be furtherimproved.

When the GW pattern of FIG. 109 is applied to, for example, thecombination of the ETRI symbol (64k, 5/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 110 is applied to, for example, thecombination of the ETRI symbol (64k, 5/15) and 16QAM of FIG. 90, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 111 is applied to, for example, thecombination of the ETRI symbol (64k, 5/15) and 64QAM of FIG. 91, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 112 is applied to, for example, thecombination of the Sony symbol (64k, 7/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 113 is applied to, for example, thecombination of the Sony symbol (64k, 7/15) and 16QAM of FIG. 90, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 114 is applied to, for example, thecombination of the Sony symbol (64k, 7/15) and 64QAM of FIG. 91, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 115 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 116 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and 16QAM of FIG. 90, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 117 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and 64QAM of FIG. 91, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 118 is applied to, for example, thecombination of the Sony symbol (64k, 11/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 119 is applied to, for example, thecombination of the Sony symbol (64k, 11/15) and 16QAM of FIG. 90, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 120 is applied to, for example, thecombination of the Sony symbol (64k, 11/15) and 64QAM of FIG. 91, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 121 is applied to, for example, thecombination of the Sony symbol (64k, 13/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 122 is applied to, for example, thecombination of the Sony symbol (64k, 13/15) and 16QAM of FIG. 90, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 123 is applied to, for example, thecombination of the Sony symbol (64k, 13/15) and 64QAM of FIG. 91, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 124 is applied to, for example, thecombination of the ETRI symbol (64k, 5/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 125 is applied to, for example, thecombination of the ETRI symbol (64k, 7/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 126 is applied to, for example, thecombination of the Sony symbol (64k, 7/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 127 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 128 is applied to, for example, thecombination of the NERC symbol (64k, 9/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 129 is applied to, for example, thecombination of the Sony symbol (64k, 11/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 130 is applied to, for example, thecombination of the Sony symbol (64k, 13/15) and 256QAM of FIGS. 92 and93, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 131 is applied to, for example, thecombination of the ETRI symbol (64k, 5/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 132 is applied to, for example, thecombination of the ETRI symbol (64k, 7/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 133 is applied to, for example, thecombination of the Sony symbol (64k, 7/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 134 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 135 is applied to, for example, thecombination of the NERC symbol (64k, 9/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 136 is applied to, for example, thecombination of the Sony symbol (64k, 11/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 137 is applied to, for example, thecombination of the Sony symbol (64k, 13/15) and 1024QAM of FIGS. 94 and95, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 138 is applied to, for example, thecombination of the Samsung symbol (64k, 6/15) and 4096QAM of FIGS. 96and 97, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 139 is applied to, for example, thecombination of the ETRI symbol (64k, 7/15) and 4096QAM of FIGS. 96 and97, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 140 is applied to, for example, thecombination of the Samsung symbol (64k, 8/15) and 4096QAM of FIGS. 96and 97, a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 141 is applied to, for example, thecombination of the Sony symbol (64k, 9/15) and 4096QAM of FIGS. 96 and97, a particularly excellent error rate can be achieved.

<Example of GW Pattern for LDPC Code of 16k Bits>

FIG. 142 is an illustration of a 1st example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 142, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

21, 41, 15, 29, 0, 23, 16, 12, 38, 43, 2, 3, 4, 20, 31, 27, 5, 33, 28,30, 36, 8, 40, 13, 6, 9, 18, 24, 7, 39, 10, 17, 37, 1, 19, 22, 25, 26,14, 32, 34, 11, 35, 42, and 44.

FIG. 143 is an illustration of a 2nd example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 143, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

1, 3, 2, 8, 5, 23, 13, 12, 18, 19, 17, 20, 24, 26, 28, 30, 32, 34, 36,38, 40, 42, 0, 4, 6, 7, 21, 16, 10, 15, 9, 11, 22, 14, 25, 27, 29, 31,33, 35, 37, 39, 41, 43, and 44.

FIG. 144 is an illustration of a 3rd example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 144, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36,38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31,33, 35, 37, 39, 41, 43, and 44.

FIG. 145 is an illustration of a 4th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 145, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

3, 0, 4, 7, 18, 9, 19, 27, 32, 10, 12, 24, 8, 35, 30, 17, 22, 20, 36,38, 40, 42, 2, 5, 1, 6, 14, 15, 23, 16, 11, 21, 26, 13, 29, 33, 31, 28,25, 34, 37, 39, 41, 43, and 44.

FIG. 146 is an illustration of a 5th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 146, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

37, 0, 41, 19, 43, 8, 38, 3, 29, 13, 22, 6, 4, 2, 9, 26, 39, 15, 12, 10,33, 17, 20, 16, 21, 44, 42, 27, 7, 11, 30, 34, 24, 1, 23, 35, 36, 25,31, 18, 28, 32, 40, 5, and 14.

FIG. 147 is an illustration of a 6th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 147, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

6, 28, 17, 4, 3, 38, 13, 41, 44, 43, 7, 40, 19, 2, 23, 16, 37, 15, 30,20, 11, 8, 1, 27, 32, 34, 33, 39, 5, 9, 10, 18, 0, 31, 29, 26, 14, 21,42, 22, 12, 24, 35, 25, and 36.

FIG. 148 is an illustration of a 7th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 148, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23,16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39,43, 21, 3, 22, 26, 33, and 38.

FIG. 149 is an illustration of an 8th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 149, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16,9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43,35, 36, 13, 39, 12, 1, and 31.

FIG. 150 is an illustration of a 9th example of a GW pattern for an LDPCcode in which a code length N is 16k bits.

According to the GW pattern of FIG. 150, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

31, 38, 7, 9, 13, 21, 39, 12, 10, 1, 43, 15, 30, 0, 14, 3, 42, 34, 40,24, 28, 35, 8, 11, 23, 4, 20, 17, 41, 19, 5, 37, 22, 32, 18, 2, 26, 44,25, 33, 36, 27, 16, 6, and 29.

FIG. 151 is an illustration of a 10th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 151, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

36, 6, 2, 20, 43, 17, 33, 22, 23, 25, 13, 0, 10, 7, 21, 1, 19, 26, 8,14, 31, 35, 16, 5, 29, 40, 11, 9, 4, 34, 15, 42, 32, 28, 18, 37, 30, 39,24, 41, 3, 38, 27, 12, and 44.

FIG. 152 is an illustration of a 11th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 152, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5, 12, 24, 17, 29, 16, 39, 13, 23,8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35, 40, 32, 30, 20, 36, 31, 21, 41,44, 3, 42, 6, 19, 37, and 4.

FIG. 153 is an illustration of a 12th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 153, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

17, 11, 14, 7, 31, 10, 2, 26, 0, 32, 29, 22, 33, 12, 20, 28, 27, 39, 37,15, 4, 5, 8, 13, 38, 18, 23, 34, 24, 6, 1, 9, 16, 44, 21, 3, 36, 30, 40,35, 43, 42, 25, 19, and 41.

FIG. 154 is an illustration of a 13th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 154, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

1, 27, 17, 30, 11, 15, 9, 7, 5, 6, 32, 33, 2, 14, 3, 39, 18, 12, 29, 13,41, 31, 4, 43, 35, 34, 40, 10, 19, 44, 8, 26, 21, 16, 28, 0, 23, 38, 25,36, 22, 37, 42, 24, and 20.

FIG. 155 is an illustration of a 14th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 155, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

41, 2, 12, 6, 33, 1, 13, 11, 26, 10, 39, 43, 36, 23, 42, 7, 44, 20, 8,38, 18, 22, 24, 40, 4, 28, 29, 19, 14, 5, 9, 0, 30, 25, 35, 37, 27, 32,31, 34, 21, 3, 15, 17, and 16,

FIG. 156 is an illustration of a 15th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 156, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

17, 2, 30, 12, 7, 25, 27, 3, 15, 14, 4, 26, 34, 31, 13, 22, 0, 39, 23,24, 21, 6, 38, 5, 19, 42, 11, 32, 28, 40, 20, 18, 36, 9, 41, 10, 33, 37,1, 16, 8, 43, 29, 35, and 44.

FIG. 157 is an illustration of a 16th example of a GW pattern for anLDPC code in which a code length N is 16k bits.

According to the GW pattern of FIG. 157, a sequence of bit groups 0 to44 of the LDPC code of 16 kbits is interleaved into a sequence of bitgroups

28, 21, 10, 15, 8, 22, 26, 2, 14, 1, 27, 3, 39, 20, 34, 25, 12, 6, 7,40, 30, 29, 38, 16, 43, 33, 4, 35, 9, 32, 5, 36, 0, 41, 37, 18, 17, 13,24, 42, 31, 23, 19, 11, and 44.

The 1st to 16th examples of the GW pattern for the LDPC code in whichthe code length N is 16 kbits can be applied to any combination of theLDPC code in which the code length N is 16 kbits with an arbitraryencoding rate r and modulation scheme (constellation).

However, when the GW pattern to be applied to the group-wise interleaveis set for each combination of the code length N of the LDPC code, theencoding rate r of the LDPC code, and the modulation scheme(constellation), the error rate of each combination can be furtherimproved.

When the GW pattern of FIG. 142 is applied to, for example, thecombination of the LGE symbol (16k, 6/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 143 is applied to, for example, thecombination of the Sony symbol (16k, 8/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 144 is applied to, for example, thecombination of the Sony symbol (16k, 10/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 145 is applied to, for example, thecombination of the Sony symbol (16k, 12/15) and QPSK of FIG. 89, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 146 is applied to, for example, thecombination of the LGE symbol (16k, 6/15) and 16QAM of FIG. 101, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 147 is applied to, for example, thecombination of the Sony symbol (16k, 8/15) and 16QAM of FIG. 101, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 148 is applied to, for example, thecombination of the Sony symbol (16k, 10/15) and 16QAM of FIG. 101, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 149 is applied to, for example, thecombination of the Sony symbol (16k, 12/15) and 16QAM of FIG. 101, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 150 is applied to, for example, thecombination of the LGE symbol (16k, 6/15) and 64QAM of FIG. 102, aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 151 is applied to, for example, thecombination of the Sony symbol (16k, 8/15) and 64QAM of FIG. 102 aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 152 is applied to, for example, thecombination of the Sony symbol (16k, 10/15) and 64QAM of FIG. 102 aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 153 is applied to, for example, thecombination of the Sony symbol (16k, 12/15) and 64QAM of FIG. 102 aparticularly excellent error rate can be achieved.

When the GW pattern of FIG. 154 is applied to, for example, thecombination of the LGE symbol (16k, 6/15) and 256QAM of FIGS. 103 and104 a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 155 is applied to, for example, thecombination of the Sony symbol (16k, 8/15) and 256QAM of FIGS. 103 and104 a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 156 is applied to, for example, thecombination of the Sony symbol (16k, 10/15) and 256QAM of FIGS. 103 and104 a particularly excellent error rate can be achieved.

When the GW pattern of FIG. 157 is applied to, for example, thecombination of the Sony symbol (16k, 12/15) and 256QAM of FIGS. 103 and104 a particularly excellent error rate can be achieved.

<Simulation Result>

FIG. 158 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 109 is applied to a combination of the ETRI symbol (64k, 5/15)and QPSK of FIG. 89.

FIG. 159 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 110 is applied to a combination of the ETRI symbol (64k, 5/15)and 16QAM of FIG. 90.

FIG. 160 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 111 is applied to a combination of the ETRI symbol (64k, 5/15)and 64QAM of FIG. 91.

FIG. 161 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 112 is applied to a combination of the Sony symbol (64k, 7/15)and QPSK of FIG. 89.

FIG. 162 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 113 is applied to a combination of the Sony symbol (64k, 7/15)and 16QAM of FIG. 90.

FIG. 163 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 114 is applied to a combination of the Sony symbol (64k, 7/15)and 64QAM of FIG. 91.

FIG. 164 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 115 is applied to a combination of the Sony symbol (64k, 9/15)and QPSK of FIG. 89.

FIG. 165 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 116 is applied to a combination of the Sony symbol (64k, 9/15)and 16QAM of FIG. 90.

FIG. 166 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 117 is applied to a combination of the Sony symbol (64k, 9/15)and 64QAM of FIG. 91.

FIG. 167 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 118 is applied to a combination of the Sony symbol (64k, 11/15)and QPSK of FIG. 89.

FIG. 168 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 119 is applied to a combination of the Sony symbol (64k, 11/15)and 16QAM of FIG. 90.

FIG. 169 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 120 is applied to a combination of the Sony symbol (64k, 11/15)and 64QAM of FIG. 91.

FIG. 170 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 121 is applied to a combination of the Sony symbol (64k, 13/15)and QPSK of FIG. 89.

FIG. 171 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 122 is applied to a combination of the Sony symbol (64k, 13/15)and 16QAM of FIG. 90.

FIG. 172 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 123 is applied to a combination of the Sony symbol (64k, 13/15)and 64QAM of FIG. 91.

FIG. 173 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 124 is applied to a combination of the ETRI symbol (64k, 5/15)and 256QAM of FIGS. 92 and 93.

FIG. 174 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 125 is applied to a combination of the ETRI symbol (64k, 7/15)and 256QAM of FIGS. 92 and 93.

FIG. 175 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 126 is applied to a combination of the Sony symbol (64k, 7/15)and 256QAM of FIGS. 92 and 93.

FIG. 176 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 127 is applied to a combination of the Sony symbol (64k, 9/15)and 256QAM of FIGS. 92 and 93.

FIG. 177 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 128 is applied to a combination of the NERC symbol (64k, 9/15)and 256QAM of FIGS. 92 and 93.

FIG. 178 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 129 is applied to a combination of the Sony symbol (64k, 9/15)and 256QAM of FIGS. 92 and 93.

FIG. 179 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 130 is applied to a combination of the Sony symbol (64k, 13/15)and 256QAM of FIGS. 92 and 93.

FIG. 180 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 131 is applied to a combination of the ETRI symbol (64k, 5/15)and 1024QAM of FIGS. 94 and 95.

FIG. 181 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 132 is applied to a combination of the ETRI symbol (64k, 7/15)and 1024QAM of FIGS. 94 and 95.

FIG. 182 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 133 is applied to a combination of the Sony symbol (64k, 7/15)and 1024QAM of FIGS. 94 and 95.

FIG. 183 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 134 is applied to a combination of the Sony symbol (64k, 9/15)and 1024QAM of FIGS. 94 and 95.

FIG. 184 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 135 is applied to a combination of the NERC symbol (64k, 9/15)and 1024QAM of FIGS. 94 and 95.

FIG. 185 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 136 is applied to a combination of the Sony symbol (64k, 11/15)and 1024QAM of FIGS. 94 and 95.

FIG. 186 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 137 is applied to a combination of the Sony symbol (64k, 13/15)and 1024QAM of FIGS. 94 and 95.

FIG. 187 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 138 is applied to a combination of the Samsung symbol (64k,6/15) and 4096QAM of FIGS. 96 and 97.

FIG. 188 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 139 is applied to a combination of the ETRI symbol (64k, 7/15)and 4096QAM of FIGS. 96 and 97.

FIG. 189 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 140 is applied to a combination of the Samsung symbol (64k,8/15) and 4096QAM of FIGS. 96 and 97.

FIG. 190 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 141 is applied to a combination of the Sony symbol (64k, 9/15)and 4096QAM of FIGS. 96 and 97.

FIG. 191 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 142 is applied to a combination of the LGE symbol (16k, 6/15)and QPSK of FIG. 89.

FIG. 192 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 143 is applied to a combination of the Sony symbol (16k, 8/15)and QPSK of FIG. 89.

FIG. 193 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 144 is applied to a combination of the Sony symbol (16k, 10/15)and QPSK of FIG. 89.

FIG. 194 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 145 is applied to a combination of the Sony symbol (16k, 12/15)and QPSK of FIG. 89.

FIG. 195 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 146 is applied to a combination of the LGE symbol (16k, 6/15)and 16QAM of FIG. 101.

FIG. 196 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 147 is applied to a combination of the Sony symbol (16k, 8/15)and 16QAM of FIG. 101.

FIG. 197 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 148 is applied to a combination of the Sony symbol (16k, 10/15)and 16QAM of FIG. 101.

FIG. 198 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 149 is applied to a combination of the Sony symbol (16k, 12/15)and 16QAM of FIG. 101.

FIG. 199 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 150 is applied to a combination of the LGE symbol (16k, 6/15)and 64QAM of FIG. 102.

FIG. 200 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 151 is applied to a combination of the Sony symbol (16k, 8/15)and 64QAM of FIG. 102.

FIG. 201 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 152 is applied to a combination of the Sony symbol (16k, 10/15)and 64QAM of FIG. 102.

FIG. 202 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 153 is applied to a combination of the Sony symbol (16k, 12/15)and 64QAM of FIG. 102.

FIG. 203 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 154 is applied to a combination of the LGE symbol (16k, 6/15)and 256QAM of FIGS. 103 and 104.

FIG. 204 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 155 is applied to a combination of the Sony symbol (16k, 8/15)and 256QAM of FIGS. 103 and 104.

FIG. 205 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 156 is applied to a combination of the Sony symbol (16k, 10/15)and 256QAM of FIGS. 103 and 104.

FIG. 206 is an illustration of a BER/FER curve indicating a simulationresult of a simulation of measuring the error rate when the GW patternof FIG. 157 is applied to a combination of the Sony symbol (16k, 12/15)and 256QAM of FIGS. 103 and 104.

FIGS. 158 to 206 illustrate BER/FER curves when an AWGN channel isemployed as the communication path 13 (FIG. 7) (the upper drawings) andBER/FER curves when a Rayleigh (fading) channel is employed as thecommunication path 13 (FIG. 7) (the lower drawings).

In FIGS. 158 to 206, “w bil” indicates a BER/FER curve when the parityinterleave, the group-wise interleave, and the block-wise interleave areperformed, and “w/o bil” indicates a BER/FER curve when the parityinterleave, the group-wise interleave, and the block-wise interleave arenot performed.

As can be seen from FIGS. 158 to 206, when the parity interleave, thegroup-wise interleave, and the block-wise interleave are performed, itis possible to improve the BER/FER and achieve the excellent the errorrate compared to when they are not performed.

Further, it is possible to apply the GW patterns of FIGS. 109 to 157 tothe constellation in which the signal point arrangements illustrated inFIGS. 83 to 104 have been moved symmetrically to the I axis or the Qaxis, the constellation in which the signal point arrangementsillustrated in FIGS. 83 to 104 have been moved symmetrically to theorigin, the constellation in which the signal point arrangementsillustrated in FIGS. 83 to 104 have been rotated at an arbitrary anglecentering on the origin, and the like in addition to the constellationof QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM of the signal pointarrangements illustrated in FIGS. 83 to 104, and it is possible toobtain the same effects as when the GW patterns of FIGS. 109 to 157 areapplied to the constellation of QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and4096QAM of the signal point arrangements illustrated in FIGS. 83 to 104.

Further, it is possible to apply the GW pattern of FIGS. 109 to 157 tothe constellation in which the most significant bit (MSB) and the leastsignificant bit (LSB) of the symbol to be associated with (allocated to)the signal point are interchanged in the signal point arrangementsillustrated in FIGS. 83 to 104 in addition to the constellation of QPSK,16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM of the signal pointarrangements illustrated in FIGS. 83 to 104, and it is possible toobtain the same effects as when the GW patterns of FIGS. 109 to 157 areapplied to the constellation of QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and4096QAM of the signal point arrangements illustrated in FIGS. 83 to 104as well.

<Configuration Example of Receiving Device 12>

FIG. 207 is a block diagram illustrating a configuration example of thereceiving device 12 of FIG. 7.

An OFDM operating unit 151 receives an OFDM signal from the transmittingdevice 11 (FIG. 7) and executes signal processing of the OFDM signal.Data that is obtained by executing the signal processing by the OFDMoperating unit 151 is supplied to a frame managing unit 152.

The frame managing unit 152 executes processing (frame interpretation)of a frame configured by the data supplied from the OFDM operating unit151 and supplies a signal of target data obtained as a result and asignal of signaling to frequency deinterleavers 161 and 153.

The frequency deinterleaver 153 performs frequency deinterleave in aunit of symbol, with respect to the data supplied from the framemanaging unit 152, and supplies the symbol to a demapper 154.

The demapper 154 performs demapping (signal point arrangement decoding)and orthogonal demodulation on the data (the data on the constellation)supplied from the frequency deinterleaver 153 based on the arrangement(constellation) of the signal points decided according to the orthogonalmodulation performed at the transmitting device 11 side, and suppliesthe data ((the likelihood of) the LDPC code) obtained as a result to theLDPC decoder 155.

The LDPC decoder 155 performs LDPC decoding of the LDPC code suppliedfrom the demapper 154 and supplies LDPC target data (in this case, a BCHcode) obtained as a result to a BCH decoder 156.

The BCH decoder 156 performs BCH decoding of the LDPC target datasupplied from the LDPC decoder 155 and outputs control data (signaling)obtained as a result.

Meanwhile, the frequency deinterleaver 161 performs frequencydeinterleave in a unit of symbol, with respect to the data supplied fromthe frame managing unit 152, and supplies the symbol to a SISO/MISOdecoder 162.

The SISO/MISO decoder 162 performs spatiotemporal decoding of the datasupplied from the frequency deinterleaver 161 and supplies the data to atime deinterleaver 163.

The time deinterleaver 163 performs time deinterleave in a unit ofsymbol, with respect to the data supplied from the SISO/MISO decoder162, and supplies the data to a demapper 164.

The demapper 164 performs demapping (signal point arrangement decoding)and orthogonal demodulation on the data (the data on the constellation)supplied from the time deinterleaver 163 based on the arrangement(constellation) of the signal points decided according to the orthogonalmodulation performed at the transmitting device 11 side, and suppliesthe data obtained as a result to a bit deinterleaver 165.

The bit deinterleaver 165 perform the bit deinterleave on the datasupplied from the demapper 164, and supplies (the likelihood of) theLDPC code serving as the data that has undergone the bit deinterleave toan LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding of the LDPC code suppliedfrom the bit deinterleaver 165 and supplies LDPC target data (in thiscase, a BCH code) obtained as a result to a BCH decoder 167.

The BCH decoder 167 performs BCH decoding of the LDPC target datasupplied from the LDPC decoder 155 and supplies data obtained as aresult to a BB descrambler 168.

The BB descrambler 168 executes BB descramble with respect to the datasupplied from the BCH decoder 167 and supplies data obtained as a resultto a null deletion unit 169.

The null deletion unit 169 deletes null inserted by the padder 112 ofFIG. 8, from the data supplied from the BB descrambler 168, and suppliesthe data to a demultiplexer 170.

The demultiplexer 170 individually separates one or more streams (targetdata) multiplexed with the data supplied from the null deletion unit169, performs necessary processing to output the streams as outputstreams.

Here, the receiving device 12 can be configured without including partof the blocks illustrated in FIG. 207. That is, for example, in a casewhere the transmitting device 11 (FIG. 8) is configured withoutincluding the time interleaver 118, the SISO/MISO encoder 119, thefrequency interleaver 120 and the frequency interleaver 124, thereceiving device 12 can be configured without including the timedeinterleaver 163, the SISO/MISO decoder 162, the frequencydeinterleaver 161 and the frequency deinterleaver 153 which are blocksrespectively corresponding to the time interleaver 118, the SISO/MISOencoder 119, the frequency interleaver 120 and the frequency interleaver124 of the transmitting device 11.

<Configuration Example of Bit Deinterleaver 165>

FIG. 208 is a block diagram illustrating a configuration example of thebit deinterleaver 165 of FIG. 207.

The bit deinterleaver 165 is configured with a block deinterleaver 54and a group-wise deinterleaver 55, and performs the (bit) deinterleaveof the symbol bits of the symbol serving as the data supplied from thedemapper 164 (FIG. 207).

In other words, the block deinterleaver 54 performs the blockdeinterleave (the inverse process of the block interleave) correspondingto the block interleave performed by the block interleaver 25 of FIG. 9,that is, the block deinterleave of restoring the positions of (thelikelihood of) of the code bits of the LDPC code rearranged by the blockinterleave to the original positions on the symbol bits of the symbolsupplied from the demapper 164, and supplies the LDPC code obtained as aresult to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs the group-wise deinterleave(the inverse process of the group-wise interleave) corresponding to thegroup-wise interleave performed by the group-wise interleaver 24 of FIG.9, that is, the group-wise deinterleave of restoring the originalsequence by rearranging the code bits of the LDPC code whose sequencehas been changed in units of bit groups by the group-wise interleavedescribed above, for example, with reference to FIG. 108 in units of bitgroups on the LDPC code supplied from the block deinterleaver 54

Here, when the LDPC code supplied from the demapper 164 to the bitdeinterleaver 165 has undergone the parity interleave, the group-wiseinterleave, and the block interleave, the bit deinterleaver 165 canperform all of the parity deinterleave (the inverse process of theparity interleave, that is, the parity deinterleave of restoring thecode bits of the LDPC code whose sequence has been changed by the parityinterleave to the original sequence) corresponding to the parityinterleave, the block deinterleave corresponding to the blockinterleave, and the group-wise deinterleave corresponding to thegroup-wise interleave.

However, the bit deinterleaver 165 of FIG. 208 is provided with theblock deinterleaver 54 that performs the block deinterleavecorresponding to the block interleave and the group-wise deinterleaver55 that performs the group-wise deinterleave corresponding to thegroup-wise interleave, but no block that performs the paritydeinterleave corresponding to the parity interleave is provided, andthus the parity deinterleave is not performed.

Thus, the LDPC code that has undergone the block deinterleave andgroup-wise deinterleave but has not undergone the parity deinterleave issupplied from (the group-wise deinterleaver 55 of) the bit deinterleaver165 to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding of the LDPC code suppliedfrom the bit deinterleaver 165 using the transformed parity check matrixobtained by performing at least the column permutation corresponding tothe parity interleave on the parity check matrix H of the DVB schemeused for the LDPC encoding by the LDPC encoder 115 of FIG. 8 (or thetransformed parity check matrix (FIG. 29) obtained by performing the rowpermutation on the parity check matrix of the ETRI scheme (FIG. 27)),and outputs data obtained as a result as a decoding result of LDPCtarget data.

FIG. 209 is a flowchart illustrating a process performed by the demapper164, the bit deinterleaver 165, and the LDPC decoder 166 of FIG. 208.

In step S111, the demapper 164 performs demapping and orthogonaldemodulation on the data (the data on the constellation mapped to thesignal points) supplied from the time deinterleaver 163, and suppliesthe resulting data to the bit deinterleaver 165, and the processproceeds to step S112.

In step S112, the bit deinterleaver 165 performs the deinterleave (thebit deinterleave) on the data supplied from the demapper 164, and theprocess proceeds to step S113.

In other words, in step S112, in the bit deinterleaver 165, the blockdeinterleaver 54 performs the block deinterleave on the data (symbol)supplied from the demapper 164, and supplies the code bits of the LDPCcode obtained as a result to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs the group-wise deinterleave onthe LDPC code supplied from the block deinterleaver 54, and supplies(the likelihood of) the LDPC code obtained as a result to the LDPCdecoder 166.

In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPCcode supplied from the group-wise deinterleaver 55 using the paritycheck matrix H used for the LDPC encoding by the LDPC encoder 115 ofFIG. 8, that is, using the transformed parity check matrix obtained fromthe parity check matrix H, for example, and outputs the data obtained asa result to the BCH decoder 167 as a decoding result of the LDPC targetdata.

In FIG. 208, similarly to the example of FIG. 9, for the sake ofconvenience of description, the block deinterleaver 54 that performs theblock deinterleave and the group-wise deinterleaver 55 that performs thegroup-wise deinterleave are configured individually, but the blockdeinterleaver 54 and the group-wise deinterleaver 55 may be configuredintegrally.

<Ldpc Decoding>

The LDPC decoding performed by the LDPC decoder 166 of FIG. 207 will bedescribed.

As described above, the LDPC decoder 166 of FIG. 207 performs the LDPCdecoding of the LDPC code that is supplied from the bit deinterleaver165 and has undergone the block deinterleave and the group-wisedeinterleave but has not undergone the parity deinterleave using thetransformed parity check matrix obtained by performing at least thecolumn permutation corresponding to the parity interleave on the paritycheck matrix H of the DVB scheme used for the LDPC encoding by the LDPCencoder 115 of FIG. 8 (or the transformed parity check matrix (FIG. 29)obtained by performing the row permutation on the parity check matrix ofthe ETRI scheme (FIG. 27)).

In this case, LDPC decoding that can suppress an operation frequency ata sufficiently realizable range while suppressing a circuit scale, byperforming the LDPC decoding using the transformed parity check matrix,is previously suggested (for example, refer to JP 4224777B).

Therefore, first, the previously suggested LDPC decoding using thetransformed parity check matrix will be described with reference toFIGS. 210 to 213.

FIG. 210 illustrates an example of a parity check matrix H of an LDPCcode in which a code length N is 90 and an encoding rate is 2/3.

In FIG. 210 (and FIGS. 211 and 212 to be described later), 0 isrepresented by a period (.).

In the parity check matrix H of FIG. 210, the parity matrix becomes astaircase structure.

FIG. 211 illustrates a parity check matrix H′ that is obtained byexecuting row replacement of an expression (11) and column replacementof an expression (12) with respect to the parity check matrix H of FIG.210.Row Replacement: (6s+t+1)-th row→(5t+s+1)-th row  (11)Column Replacement: (6x+y+61)-th column→(5y+x+61)-th column  (12)

In the expressions (11) and (12), s, t, x, and y are integers in rangesof 0≤s<5, 0≤t<6, 0≤x<5, and 0≤t<6, respectively.

According to the row replacement of the expression (11), replacement isperformed such that the 1st, 7th, 13rd, 19th, and 25th rows havingremainders of 1 when being divided by 6 are replaced with the 1st, 2nd,3rd, 4th, and 5th rows, and the 2nd, 8th, 14th, 20th, and 26th rowshaving remainders of 2 when being divided by 6 are replaced with the6th, 7th, 8th, 9th, and 10th rows, respectively.

According to the column replacement of the expression (12), replacementis performed such that the 61st, 67th, 73rd, 79th, and 85th columnshaving remainders of 1 when being divided by 6 are replaced with the61st, 62nd, 63rd, 64th, and 65th columns, respectively, and the 62nd,68th, 74th, 80th, and 86th columns having remainders of 2 when beingdivided by 6 are replaced with the 66th, 67th, 68th, 69th, and 70thcolumns, respectively, with respect to the 61st and following columns(parity matrix).

In this way, a matrix that is obtained by performing the replacements ofthe rows and the columns with respect to the parity check matrix H ofFIG. 210 is a parity check matrix H′ of FIG. 211.

In this case, even when the row replacement of the parity check matrix His performed, the sequence of the code bits of the LDPC code is notinfluenced.

The column replacement of the expression (12) corresponds to parityinterleave to interleave the (K+qx+y+1)-th code bit into the position ofthe (K+Py+x+1)-th code bit, when the information length K is 60, theunit size P is 5, and the divisor q (=M/P) of the parity length M (inthis case, 30) is 6.

Therefore, the parity check matrix H′ in FIG. 211 is a transformedparity check matrix obtained by performing at least column replacementthat replaces the K+qx+y+1-th column of the parity check matrix H inFIG. 210 (which may be arbitrarily called an original parity checkmatrix below) with the K+Py+x+1-th column.

If the parity check matrix H′ of FIG. 211 is multiplied with a resultobtained by performing the same replacement as the expression (12) withrespect to the LDPC code of the parity check matrix H of FIG. 210, azero vector is output. That is, if a row vector obtained by performingthe column replacement of the expression (12) with respect to a rowvector c as the LDPC code (one code word) of the original parity checkmatrix H is represented as c′, HcT becomes the zero vector from theproperty of the parity check matrix. Therefore, H′c′T naturally becomesthe zero vector.

Thereby, the transformed parity check matrix H′ of FIG. 211 becomes aparity check matrix of an LDPC code c′ that is obtained by performingthe column replacement of the expression (12) with respect to the LDPCcode c of the original parity check matrix H.

Therefore, the column replacement of the expression (12) is performedwith respect to the LDPC code of the original parity check matrix H, theLDPC code c′ after the column replacement is decoded (LDPC decoding)using the transformed parity check matrix H′ of FIG. 211, reversereplacement of the column replacement of the expression (12) isperformed with respect to a decoding result, and the same decodingresult as the case in which the LDPC code of the original parity checkmatrix H is decoded using the parity check matrix H can be obtained.

FIG. 212 illustrates the transformed parity check matrix H′ of FIG. 211with being spaced in units of 5×5 matrixes.

In FIG. 212, the transformed parity check matrix H′ is represented by acombination of a 5×5 (=p×p) unit matrix that is a unit size P, a matrix(hereinafter, appropriately referred to as a quasi unit matrix) obtainedby setting one or more 1 of the unit matrix to zero, a matrix(hereinafter, appropriately referred to as a shifted matrix) obtained bycyclically shifting the unit matrix or the quasi unit matrix, a sum(hereinafter, appropriately referred to as a sum matrix) of two or morematrixes of the unit matrix, the quasi unit matrix, and the shiftedmatrix, and a 5×5 zero matrix.

The transformed parity check matrix H′ of FIG. 212 can be configuredusing the 5×5 unit matrix, the quasi unit matrix, the shifted matrix,the sum matrix, and the zero matrix. Therefore, the 5×5 matrixes (theunit matrix, the quasi unit matrix, the shifted matrix, the sum matrix,and the zero matrix) that constitute the transformed parity check matrixH′ are appropriately referred to as constitutive matrixes hereinafter.

When the LDPC code represented by the parity check matrix represented bythe P×P constitutive matrixes is decoded, an architecture in which Pcheck node operations and variable node operations are simultaneouslyperformed can be used.

FIG. 213 is a block diagram illustrating a configuration example of adecoding device that performs the decoding.

That is, FIG. 213 illustrates the configuration example of the decodingdevice that performs decoding of the LDPC code, using the transformedparity check matrix H′ of FIG. 210 obtained by performing at least thecolumn replacement of the expression (12) with respect to the originalparity check matrix H of FIG. 212.

The decoding device of FIG. 213 includes a branch data storing memory300 that includes 6 FIFOs 300 ₁ to 300 ₆, a selector 301 that selectsthe FIFOs 300 ₁ to 300 ₆, a check node calculating unit 302, two cyclicshift circuits 303 and 308, a branch data storing memory 304 thatincludes 18 FIFOs 304 ₁ to 304 ₁₈, a selector 305 that selects the FIFOs304 ₁ to 304 ₁₈, a reception data memory 306 that stores reception data,a variable node calculating unit 307, a decoding word calculating unit309, a reception data rearranging unit 310, and a decoded datarearranging unit 311.

First, a method of storing data in the branch data storing memories 300and 304 will be described.

The branch data storing memory 300 includes the 6 FIFOs 300 ₁ to 300 ₆that correspond to a number obtained by dividing a row number 30 of thetransformed parity check matrix H′ of FIG. 212 by a row number 5 of theconstitutive matrix (the unit size P). The FIFO 300 _(y) (y=1, 2, . . ., and 6) includes a plurality of steps of storage regions. In thestorage region of each step, messages corresponding to five branches tobe a row number and a column number of the constitutive matrix (the unitsize P) can be simultaneously read or written. The number of steps ofthe storage regions of the FIFO 300 _(y) becomes 9 to be a maximumnumber of the number (Hamming weight) of 1 of a row direction of thetransformed parity check matrix of FIG. 212.

In the FIFO 300 ₁, data (messages v_(i) from variable nodes)corresponding to positions of 1 in the first to fifth rows of thetransformed parity check matrix H′ of FIG. 212 is stored in a formfilling each row in a transverse direction (a form in which 0 isignored). That is, if a j-th row and an i-th column are represented as(j, i), data corresponding to positions of 1 of a 5×5 unit matrix of(1, 1) to (5, 5) of the transformed parity check matrix H′ is stored inthe storage region of the first step of the FIFO 300 ₁. In the storageregion of the second step, data corresponding to positions of 1 of ashifted matrix (shifted matrix obtained by cyclically shifting the 5×5unit matrix to the right side by 3) of (1, 21) to (5, 25) of thetransformed parity check matrix H′ is stored. Similar to the above case,in the storage regions of the third to eighth steps, data is stored inassociation with the transformed parity check matrix H′. In the storageregion of the ninth step, data corresponding to positions of 1 of ashifted matrix (shifted matrix obtained by replacing 1 of the first rowof the 5×5 unit matrix with 0 and cyclically shifting the unit matrix tothe left side by 1) of (1, 86) to (5, 90) of the transformed paritycheck matrix H′ is stored.

In the FIFO 300 ₂, data corresponding to positions of 1 in the sixth totenth rows of the transformed parity check matrix H′ of FIG. 212 isstored. That is, in the storage region of the first step of the FIFO 300₂, data corresponding to positions of 1 of the first shifted matrixconstituting a sum matrix (sum matrix to be a sum of the first shiftedmatrix obtained by cyclically shifting the 5×5 unit matrix to the rightside by 1 and the second shifted matrix obtained by cyclically shiftingthe 5×5 unit matrix to the right side by 2) of (6, 1) to (10, 5) of thetransformed parity check matrix H′ is stored. In addition, in thestorage region of the second step, data corresponding to positions of 1of the second shifted matrix constituting the sum matrix of (6, 1) to(10, 5) of the transformed parity check matrix H′ is stored.

That is, with respect to a constitutive matrix of which the weight istwo or more, when the constitutive matrix is represented by a sum ofmultiple parts of a P×P unit matrix of which the weight is 1, a quasiunit matrix in which one or more elements of 1 in the unit matrix become0, or a shifted matrix obtained by cyclically shifting the unit matrixor the quasi unit matrix, data (messages corresponding to branchesbelonging to the unit matrix, the quasi unit matrix, or the shiftedmatrix) corresponding to the positions of 1 in the unit matrix of theweight of 1, the quasi unit matrix, or the shifted matrix is stored atthe same address (the same FIFO among the FIFOs 300 ₁ to 300 ₆).

Subsequently, in the storage regions of the third to ninth steps, datais stored in association with the transformed parity check matrix H′,similar to the above case.

In the FIFOs 300 ₃ to 300 ₆, data is stored in association with thetransformed parity check matrix H′, similar to the above case.

The branch data storing memory 304 includes 18 FIFOs 304 ₁ to 304 ₁₈that correspond to a number obtained by dividing a column number 90 ofthe transformed parity check matrix H′ by 5 to be a column number of aconstitutive matrix (the unit size P). The FIFO 304 _(x) (x=1, 2, . . ., and 18) includes a plurality of steps of storage regions. In thestorage region of each step, messages corresponding to five branchescorresponding to a row number and a column number of the constitutivematrix (the unit size P) can be simultaneously read or written.

In the FIFO 304 ₁, data (messages u_(j) from check nodes) correspondingto positions of 1 in the first to fifth columns of the transformedparity check matrix H′ of FIG. 212 is stored in a form filling eachcolumn in a longitudinal direction (a form in which 0 is ignored). Thatis, if a j-th row and an i-th column are represented as (j, i), datacorresponding to positions of 1 of a 5×5 unit matrix of (1, 1) to (5, 5)of the transformed parity check matrix H′ is stored in the storageregion of the first step of the FIFO 304 ₁. In the storage region of thesecond step, data corresponding to positions of 1 of the first shiftedmatrix constituting a sum matrix (sum matrix to be a sum of the firstshifted matrix obtained by cyclically shifting the 5×5 unit matrix tothe right side by 1 and the second shifted matrix obtained by cyclicallyshifting the 5×5 unit matrix to the right side by 2) of (6, 1) to (10,5) of the transformed parity check matrix H′ is stored. In addition, inthe storage region of the third step, data corresponding to positions of1 of the second shifted matrix constituting the sum matrix of (6, 1) to(10, 5) of the transformed parity check matrix H′ is stored.

That is, with respect to a constitutive matrix of which the weight istwo or more, when the constitutive matrix is represented by a sum ofmultiple parts of a P×P unit matrix of which the weight is 1, a quasiunit matrix in which one or more elements of 1 in the unit matrix become0, or a shifted matrix obtained by cyclically shifting the unit matrixor the quasi unit matrix, data (messages corresponding to branchesbelonging to the unit matrix, the quasi unit matrix, or the shiftedmatrix) corresponding to the positions of 1 in the unit matrix of theweight of 1, the quasi unit matrix, or the shifted matrix is stored atthe same address (the same FIFO among the FIFOs 304 ₁ to 304 ₁₈).

Subsequently, in the storage regions of the fourth and fifth steps, datais stored in association with the transformed parity check matrix H′,similar to the above case. The number of steps of the storage regions ofthe FIFO 304 ₁ becomes 5 to be a maximum number of the number (Hammingweight) of 1 of a row direction in the first to fifth columns of thetransformed parity check matrix H′.

In the FIFOs 304 ₂ and 304 ₃, data is stored in association with thetransformed parity check matrix H′, similar to the above case, and eachlength (the number of steps) is 5. In the FIFOs 304 ₄ to 304 ₁₂, data isstored in association with the transformed parity check matrix H′,similar to the above case, and each length is 3. In the FIFOs 304 ₁₃ to304 ₁₈, data is stored in association with the transformed parity checkmatrix H′, similar to the above case, and each length is 2.

Next, an operation of the decoding device of FIG. 213 will be described.

The branch data storing memory 300 includes the 6 FIFOs 300 ₁ to 300 ₆.According to information (matrix data) D312 on which row of thetransformed parity check matrix H′ in FIG. 212 five messages D311supplied from a cyclic shift circuit 308 of a previous step belongs to,the FIFO storing data is selected from the FIFOs 300 ₁ to 300 ₆ and thefive messages D311 are collectively stored sequentially in the selectedFIFO. When the data is read, the branch data storing memory 300sequentially reads the five messages D300 ₁ from the FIFO 300 ₁ andsupplies the messages to the selector 301 of a next step. After readingof the messages from the FIFO 300 ₁ ends, the branch data storing memory300 reads the messages sequentially from the FIFOs 300 ₂ to 300 ₆ andsupplies the messages to the selector 301.

The selector 301 selects the five messages from the FIFO from which datais currently read, among the FIFOs 300 ₁ to 300 ₆, according to a selectsignal D301, and supplies the selected messages as messages D302 to thecheck node calculating unit 302.

The check node calculating unit 302 includes five check node calculators302 ₁ to 302 ₅. The check node calculating unit 302 performs a checknode operation according to the expression (7), using the messages D302(D302 ₁ to D302 ₅) (messages v_(i) of the expression 7) supplied throughthe selector 301, and supplies five messages D303 (D303 ₁ to D303 ₅)(messages u_(j) of the expression (7)) obtained as a result of the checknode operation to a cyclic shift circuit 303.

The cyclic shift circuit 303 cyclically shifts the five messages D303 ₁to D303 ₅ calculated by the check node calculating unit 302, on thebasis of information (matrix data) D305 on how many the unit matrixes(or the quasi unit matrix) becoming the origin in the transformed paritycheck matrix H′ are cyclically shifted to obtain the correspondingbranches, and supplies a result as messages D304 to the branch datastoring memory 304.

The branch data storing memory 304 includes the eighteen FIFOs 304 ₁ to304 ₁₈. According to information D305 on which row of the transformedparity check matrix H′ five messages D304 supplied from a cyclic shiftcircuit 303 of a previous step belongs to, the FIFO storing data isselected from the FIFOs 304 ₁ to 304 ₁₈ and the five messages D304 arecollectively stored sequentially in the selected FIFO. When the data isread, the branch data storing memory 304 sequentially reads the fivemessages D304 ₁ from the FIFO 304 ₁ and supplies the messages to theselector 305 of a next step. After reading of the messages from the FIFO304 ₁ ends, the branch data storing memory 304 reads the messagessequentially from the FIFOs 304 ₂ to 304 ₁₈ and supplies the messages tothe selector 305.

The selector 305 selects the five messages from the FIFO from which datais currently read, among the FIFOs 304 ₁ to 304 ₁₈, according to aselect signal D307, and supplies the selected messages as messages D308to the variable node calculating unit 307 and the decoding wordcalculating unit 309.

Meanwhile, the reception data rearranging unit 310 rearranges the LDPCcode D313, that is corresponding to the parity check matrix H in FIG.210, received through the communication path 13 by performing the columnreplacement of the expression (12) and supplies the LDPC code asreception data D314 to the reception data memory 306. The reception datamemory 306 calculates a reception LLR (Log Likelihood Ratio) from thereception data D314 supplied from the reception data rearranging unit310, stores the reception LLR, collects five reception LLRs, andsupplies the reception LLRs as reception values D309 to the variablenode calculating unit 307 and the decoding word calculating unit 309.

The variable node calculating unit 307 includes five variable nodecalculators 307 ₁ to 307 ₅. The variable node calculating unit 307performs the variable node operation according to the expression (1),using the messages D308 (D308 ₁ to D308 ₅) (messages u_(j) of theexpression (1)) supplied through the selector 305 and the five receptionvalues D309 (reception values u_(0i) of the expression (1)) suppliedfrom the reception data memory 306, and supplies messages D310 (D310 ₁to D310 ₅) (message v_(i) of the expression (1)) obtained as anoperation result to the cyclic shift circuit 308.

The cyclic shift circuit 308 cyclically shifts the messages D310 ₁ toD310 ₅ calculated by the variable node calculating unit 307, on thebasis of information on how many the unit matrixes (or the quasi unitmatrix) becoming the origin in the transformed parity check matrix H′are cyclically shifted to obtain the corresponding branches, andsupplies a result as messages D311 to the branch data storing memory300.

By circulating the above operation in one cycle, decoding (variable nodeoperation and check node operation) of the LDPC code can be performedonce. After decoding the LDPC code by the predetermined number of times,the decoding device of FIG. 213 calculates a final decoding result andoutputs the final decoding result, in the decoding word calculating unit309 and the decoded data rearranging unit 311.

That is, the decoding word calculating unit 309 includes five decodingword calculators 309 ₁ to 309 ₅. The decoding word calculating unit 309calculates a decoding result (decoding word) on the basis of theexpression (5), as a final step of multiple decoding, using the fivemessages D308 (D308 ₁ to D308 ₅) (messages u_(j) of the expression)output by the selector 305 and the five reception values D309 (receptionvalues u_(0i) of the expression (5)) supplied from the reception datamemory 306, and supplies decoded data D315 obtained as a result to thedecoded data rearranging unit 311.

The decoded data rearranging unit 311 performs the reverse replacementof the column replacement of the expression (12) with respect to thedecoded data D315 supplied from the decoding word calculating unit 309,rearranges the order thereof, and outputs the decoded data as a finaldecoding result D316.

As mentioned above, by performing one or both of row replacement andcolumn replacement on the parity check matrix (original parity checkmatrix) and converting it into a parity check matrix (transformed paritycheck matrix) that can be shown by the combination of a p×p unit matrix,a quasi unit matrix in which one or more elements of 1 thereof become 0,a shifted matrix that cyclically shifts the unit matrix or the quasiunit matrix, a sum matrix that is the sum of two or more of the unitmatrix, the quasi unit matrix and the shifted matrix, and a p×p 0matrix, that is, the combination of constitutive matrixes, as for LDPCcode decoding, it becomes possible to adopt architecture thatsimultaneously performs check node calculation and variable nodecalculation by P which is the number less than the row number and columnnumber of the parity check matrix. In the case of adopting thearchitecture that simultaneously performs node calculation (check nodecalculation and variable node calculation) by P which is the number lessthan the row number and column number of the parity check matrix, ascompared with a case where the node calculation is simultaneouslyperformed by the number equal to the row number and column number of theparity check matrix, it is possible to suppress the operation frequencywithin a feasible range and perform many items of iterative decoding.

The LDPC decoder 166 that constitutes the receiving device 12 of FIG.207 performs the LDPC decoding by simultaneously performing P check nodeoperations and variable node operations, similar to the decoding deviceof FIG. 213.

That is, for the simplification of explanation, if the parity checkmatrix of the LDPC code output by the LDPC encoder 115 constituting thetransmitting device 11 of FIG. 8 is regarded as the parity check matrixH illustrated in FIG. 210 in which the parity matrix becomes a staircasestructure, in the parity interleaver 23 of the transmitting device 11,the parity interleave to interleave the (K+qx+y+1)-th code bit into theposition of the (K+Py+x+1)-th code bit is performed in a state in whichthe information K is set to 60, the unit size P is set to 5, and thedivisor q (=M/P) of the parity length M is set to 6.

Because the parity interleave corresponds to the column replacement ofthe expression (12) as described above, it is not necessary to performthe column replacement of the expression (12) in the LDPC decoder 166.

For this reason, in the receiving device 12 of FIG. 207, as describedabove, the LDPC code in which the parity deinterleave is not performed,that is, the LDPC code in a state in which the column replacement of theexpression (12) is performed is supplied from the group-wisedeinterleaver 55 to the LDPC decoder 166. In the LDPC decoder 166, thesame processing as the decoding device of FIG. 213, except that thecolumn replacement of the expression (12) is not performed, is executed.

That is, FIG. 214 illustrates a configuration example of the LDPCdecoder 166 of FIG. 207.

In FIG. 214, the LDPC decoder 166 has the same configuration as thedecoding device of FIG. 213, except that the reception data rearrangingunit 310 of FIG. 213 is not provided, and executes the same processingas the decoding device of FIG. 213, except that the column replacementof the expression (12) is not performed. Therefore, explanation of theLDPC decoder is omitted.

As described above, because the LDPC decoder 166 can be configuredwithout providing the reception data rearranging unit 310, a scale canbe decreased as compared with the decoding device of FIG. 213.

In FIGS. 210 to 214, for the simplification of explanation, the codelength N of the LDPC code is set to 90, the information length K is setto 60, the unit size (the row number and the column number of theconstitutive matrix) P is set to 5, and the divisor q (=M/P) of theparity length M is set to 6. However, the code length N, the informationlength K, the unit size P, and the divisor q (=M/P) are not limited tothe above values.

That is, in the transmitting device 11 of FIG. 8, the LDPC encoder 115outputs the LDPC code in which the code length N is set to 64800 or16200, the information length K is set to N−Pq (=N−M), the unit size Pis set to 360, and the divisor q is set to M/P. However, the LDPCdecoder 166 of FIG. 214 can be applied to the case in which P check nodeoperation and variable node operations are simultaneously performed withrespect to the LDPC code and the LDPC decoding is performed.

Further, when the parity portion of the decoding result is unnecessary,and only the information bits of the decoding result are output afterthe decoding of the LDPC code by the LDPC decoder 166, the LDPC decoder166 may be configured without the decoded data rearranging unit 311.

<Configuration Example of Block Deinterleaver 54>

FIG. 215 is a block diagram illustrating a configuration example of theblock deinterleaver 54 of FIG. 208.

The block deinterleaver 54 has a similar configuration to the blockinterleaver 25 described above with reference to FIG. 105.

Thus, the block deinterleaver 54 includes the storage region called thepart 1 and the storage region called the part 2, and each of the parts 1and 2 is configured such that a number C of columns equal in number tothe number m of bits of the symbol and serving as storage regions thatstore one bit in the row (horizontal) direction and store apredetermined number of bits in the column (vertical) direction arearranged.

The block deinterleaver 54 performs the block deinterleave by writingthe LDPC code in the parts 1 and 2 and reading the LDPC code from theparts 1 and 2.

However, in the block deinterleave, the writing of the LDPC code(serving as the symbol) is performed in the order in which the LDPC codeis read by the block interleaver 25 of FIG. 105.

Further, in the block deinterleave, the reading of the LDPC code isperformed in the order in which the LDPC code is written by the blockinterleaver 25 of FIG. 105.

In other words, in the block interleave performed by the blockinterleaver 25 of FIG. 105, the LDPC code is written in the parts 1 and2 in the column direction and read from the parts 1 and 2 in the rowdirection, but in the block deinterleave performed by the blockdeinterleaver 54 of FIG. 215, the LDPC code is written in the parts 1and 2 in the row direction and read from the parts 1 and 2 in the columndirection.

<Other Configuration Example of Bit Deinterleaver 165>

FIG. 216 is a block diagram illustrating another configuration exampleof the bit deinterleaver 165 of FIG. 217.

In the drawings, portions that correspond to the case of FIG. 208 aredenoted with the same reference numerals and explanation thereof isappropriately omitted hereinafter.

That is, the bit deinterleaver 165 of FIG. 216 has the sameconfiguration as the case of FIG. 208, except that a paritydeinterleaver 1011 is newly provided.

Referring to FIG. 216, the bit deinterleaver 165 is configured with ablock deinterleaver 54, a group-wise deinterleaver 55, and a paritydeinterleaver 1011, and performs the bit deinterleave on the code bitsof the LDPC code supplied from the demapper 164.

In other words, the block deinterleaver 54 performs the blockdeinterleave (the inverse process of the block interleave) correspondingto the block interleave performed by the block interleaver 25 of thetransmitting device 11, that is, the block deinterleave of restoring thepositions of the code bits rearranged by the block interleave to theoriginal positions on the LDPC code supplied from the demapper 164, andsupplies the LDPC code obtained as a result to the group-wisedeinterleaver 55.

The group-wise deinterleaver 55 performs the group-wise deinterleavecorresponding to the group-wise interleave serving as the rearrangementprocess performed by the group-wise interleaver 24 of the transmittingdevice 11 on the LDPC code supplied from the block deinterleaver 54.

The LDPC code that is obtained as a result of the group-wisedeinterleave is supplied from the group-wise deinterleaver 55 to theparity deinterleaver 1011.

The parity deinterleaver 1011 performs the parity deinterleave (reverseprocessing of the parity interleave) corresponding to the parityinterleave performed by the parity interleaver 23 of the transmittingdevice 11, that is, the parity deinterleave to restore the sequence ofthe code bits of the LDPC code of which a sequence is changed by theparity interleave to the original sequence, with respect to the codebits after the group-wise deinterleave in the group-wise deinterleaver55.

The LDPC code that is obtained as a result of the parity deinterleave issupplied from the parity deinterleaver 1011 to the LDPC decoder 166.

Therefore, in the bit deinterleaver 165 of FIG. 216, the LDPC code inwhich the block deinterleave, the group-wise deinterleave, and theparity deinterleave are performed, that is, the LDPC code that isobtained by the LDPC encoding according to the parity check matrix H issupplied to the LDPC decoder 166.

The LDPC decoder 166 performs the LDPC decoding of the LDPC codesupplied from the bit deinterleaver 165 using the parity check matrix Hused for the LDPC encoding by the LDPC encoder 115 of the transmittingdevice 11. In other words, the LDPC decoder 166 performs the LDPCdecoding of the LDPC code supplied from the bit deinterleaver 165 usingthe parity check matrix H (of the DVB scheme) used for the LDPC encodingby the LDPC encoder 115 of the transmitting device 11 or the transformedparity check matrix obtained by performing at least the columnpermutation corresponding to the parity interleave on the parity checkmatrix H (for the ETRI scheme, the parity check matrix (FIG. 28)obtained by performing the column permutation on the parity check matrix(FIG. 27) used for the LDPC encoding or the transformed parity checkmatrix (FIG. 29) obtained by performing the row permutation on theparity check matrix (FIG. 27) used for the LDPC encoding).

In FIG. 216, the LDPC code that is obtained by the LDPC encodingaccording to the parity check matrix H is supplied from (the paritydeinterleaver 1011 of) the bit deinterleaver 165 to the LDPC decoder166. For this reason, when the LDPC decoding of the LDPC code isperformed using the parity check matrix H (of the DVB method) itselfused by the LDPC encoder 115 of the transmitting device 11 to performthe LDPC encoding (for the ETRI scheme, the parity check matrix (FIG.28) obtained by performing the column permutation on the parity checkmatrix (FIG. 27) used for the LDPC encoding), the LDPC decoder 166 canbe configured by a decoding device performing the LDPC decodingaccording to a full serial decoding method to sequentially performoperations of messages (a check node message and a variable nodemessage) for each node or a decoding device performing the LDPC decodingaccording to a full parallel decoding method to simultaneously (inparallel) perform operations of messages for all nodes.

In the LDPC decoder 166, when the LDPC decoding of the LDPC code isperformed using the transformed parity check matrix obtained byperforming at least the column replacement corresponding to the parityinterleave with respect to the parity check matrix H (of the DVB method)used by the LDPC encoder 115 of the transmitting device 11 to performthe LDPC encoding (for the ETRI scheme, the transformed parity checkmatrix (FIG. 29) obtained by performing the row permutation on theparity check matrix (FIG. 27) used for the LDPC encoding), the LDPCdecoder 166 can be configured by a decoding device (FIG. 213) that is adecoding device of an architecture simultaneously performing P (ordivisor of P other than 1) check node operations and variable nodeoperations and has the reception data rearranging unit 310 to performthe same column replacement as the column replacement (parityinterleave) to obtain the transformed parity check matrix with respectto the LDPC code and rearrange the code bits of the LDPC code.

In FIG. 216, for the sake of convenience of description, the blockdeinterleaver 54 that performs the block deinterleave, the group-wisedeinterleaver 55 that performs the group-wise deinterleave, and theparity deinterleaver 1011 that performs the parity deinterleave areconfigured individually, but two or more of the block deinterleaver 54,the group-wise deinterleaver 55, and the parity deinterleaver 1011 maybe configured integrally, similarly to the parity interleaver 23, thegroup-wise interleaver 24, and the block interleaver 25 of thetransmitting device 11.

<Configuration Example of Reception System>

FIG. 217 is a block diagram illustrating a first configuration exampleof a reception system that can be applied to the receiving device 12.

In FIG. 217, the reception system includes an acquiring unit 1101, atransmission path decoding processing unit 1102, and an informationsource decoding processing unit 1103.

The acquiring unit 1101 acquires a signal including an LDPC codeobtained by performing at least LDPC encoding with respect to LDPCtarget data such as image data or sound data of a program, through atransmission path (communication path) not illustrated in the drawings,such as terrestrial digital broadcasting, satellite digitalbroadcasting, a CATV network, the Internet, or other networks, andsupplies the signal to the transmission path decoding processing unit1102.

In this case, when the signal acquired by the acquiring unit 1101 isbroadcast from a broadcasting station through a ground wave, a satellitewave, or a CATV (Cable Television) network, the acquiring unit 1101 isconfigured using a tuner and an STB (Set Top Box). When the signalacquired by the acquiring unit 1101 is transmitted from a web server bymulticasting like an IPTV (Internet Protocol Television), the acquiringunit 1101 is configured using a network I/F (Interface) such as an NIC(Network Interface Card).

The transmission path decoding processing unit 1102 corresponds to thereceiving device 12. The transmission path decoding processing unit 1102executes transmission path decoding processing including at leastprocessing for correcting error generated in a transmission path, withrespect to the signal acquired by the acquiring unit 1101 through thetransmission path, and supplies a signal obtained as a result to theinformation source decoding processing unit 1103.

That is, the signal that is acquired by the acquiring unit 1101 throughthe transmission path is a signal that is obtained by performing atleast error correction encoding to correct the error generated in thetransmission path. The transmission path decoding processing unit 1102executes transmission path decoding processing such as error correctionprocessing, with respect to the signal.

As the error correction encoding, for example, LDPC encoding or BCHencoding exists. In this case, as the error correction encoding, atleast the LDPC encoding is performed.

The transmission path decoding processing includes demodulation of amodulation signal.

The information source decoding processing unit 1103 executesinformation source decoding processing including at least processing forextending compressed information to original information, with respectto the signal on which the transmission path decoding processing isexecuted.

That is, compression encoding that compresses information may beperformed with respect to the signal acquired by the acquiring unit 1101through the transmission path to decrease a data amount of an image or asound corresponding to information. In this case, the information sourcedecoding processing unit 1103 executes the information source decodingprocessing such as the processing (extension processing) for extendingthe compressed information to the original information, with respect tothe signal on which the transmission path decoding processing isexecuted.

When the compression encoding is not performed with respect to thesignal acquired by the acquiring unit 1101 through the transmissionpath, the processing for extending the compressed information to theoriginal information is not executed in the information source decodingprocessing unit 1103.

In this case, as the extension processing, for example, MPEG decodingexists. In the transmission path decoding processing, in addition to theextension processing, descramble may be included.

In the reception system that is configured as described above, in theacquiring unit 1101, a signal in which the compression encoding such asthe MPEG encoding and the error correction encoding such as the LDPCencoding are performed with respect to data such as an image or a soundis acquired through the transmission path and is supplied to thetransmission path decoding processing unit 1102.

In the transmission path decoding processing unit 1102, the sameprocessing as the receiving device 12 executes as the transmission pathdecoding processing with respect to the signal supplied from theacquiring unit 1101 and a signal obtained as a result is supplied to theinformation source decoding processing unit 1103.

In the information source decoding processing unit 1103, the informationsource decoding processing such as the MPEG decoding is executed withrespect to the signal supplied from the transmission path decodingprocessing unit 1102 and an image or a sound obtained as a result isoutput.

The reception system of FIG. 217 described above can be applied to atelevision tuner to receive television broadcasting corresponding todigital broadcasting.

Each of the acquiring unit 1101, the transmission path decodingprocessing unit 1102, and the information source decoding processingunit 1103 can be configured as one independent device (hardware (IC(Integrated Circuit) and the like) or software module).

With respect to the acquiring unit 1101, the transmission path decodingprocessing unit 1102, and the information source decoding processingunit 1103, each of a set of the acquiring unit 1101 and the transmissionpath decoding processing unit 1102, a set of the transmission pathdecoding processing unit 1102 and the information source decodingprocessing unit 1103, and a set of the acquiring unit 1101, thetransmission path decoding processing unit 1102, and the informationsource decoding processing unit 1103 can be configured as oneindependent device.

FIG. 218 is a block diagram illustrating a second configuration exampleof the reception system that can be applied to the receiving device 12.

In the drawings, portions that correspond to the case of FIG. 217 aredenoted with the same reference numerals and explanation thereof isappropriately omitted hereinafter.

The reception system of FIG. 218 is common to the case of FIG. 217 inthat the acquiring unit 1101, the transmission path decoding processingunit 1102, and the information source decoding processing unit 1103 areprovided and is different from the case of FIG. 217 in that an outputunit 1111 is newly provided.

The output unit 1111 is a display device to display an image or aspeaker to output a sound and outputs an image or a sound correspondingto a signal output from the information source decoding processing unit1103. That is, the output unit 1111 displays the image or outputs thesound.

The reception system of FIG. 218 described above can be applied to a TV(television receiver) receiving television broadcasting corresponding todigital broadcasting or a radio receiver receiving radio broadcasting.

When the compression encoding is not performed with respect to thesignal acquired in the acquiring unit 1101, the signal that is output bythe transmission path decoding processing unit 1102 is supplied to theoutput unit 1111.

FIG. 219 is a block diagram illustrating a third configuration exampleof the reception system that can be applied to the receiving device 12.

In the drawings, portions that correspond to the case of FIG. 217 aredenoted with the same reference numerals and explanation thereof isappropriately omitted hereinafter.

The reception system of FIG. 219 is common to the case of FIG. 217 inthat the acquiring unit 1101 and the transmission path decodingprocessing unit 1102 are provided.

However, the reception system of FIG. 219 is different from the case ofFIG. 217 in that the information source decoding processing unit 1103 isnot provided and a recording unit 1121 is newly provided.

The recording unit 1121 records (stores) a signal (for example, TSpackets of TS of MPEG) output by the transmission path decodingprocessing unit 1102 on recording (storage) media such as an opticaldisk, a hard disk (magnetic disk), and a flash memory.

The reception system of FIG. 219 described above can be applied to arecorder that records television broadcasting.

In FIG. 219, the reception system is configured by providing theinformation source decoding processing unit 1103 and can record thesignal obtained by executing the information source decoding processingby the information source decoding processing unit 1103, that is, theimage or the sound obtained by decoding, by the recording unit 1121.

<Embodiment of Computer>

Next, the series of processing described above can be executed byhardware or can be executed by software. In the case in which the seriesof processing is executed by the software, a program configuring thesoftware is installed in a general-purpose computer.

Therefore, FIG. 220 illustrates a configuration example of an embodimentof the computer in which a program executing the series of processing isinstalled.

The program can be previously recorded on a hard disk 705 and a ROM 703corresponding to recording media embedded in the computer.

Alternatively, the program can be temporarily or permanently stored(recorded) on removable recording media 711 such as a flexible disk, aCD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, aDVD (Digital Versatile Disc), a magnetic disk, and a semiconductormemory. The removable recording media 711 can be provided as so-calledpackage software.

The program is installed from the removable recording media 711 to thecomputer. In addition, the program can be transmitted from a downloadsite to the computer by wireless through an artificial satellite fordigital satellite broadcasting or can be transmitted to the computer bywire through a network such as a LAN (Local Area Network) or theInternet. The computer can receive the program transmitted as describedabove by a communication unit 708 and install the program in theembedded hard disk 705.

The computer includes a CPU (Central Processing Unit) 702 embeddedtherein. An input/output interface 710 is connected to the CPU 702through a bus 701. If a user operates an input unit 707 configured usinga keyboard, a mouse, and a microphone and a command is input through theinput/output interface 710, the CPU 702 executes the program stored inthe ROM (Read Only Memory) 703, according to the command. Alternatively,the CPU 702 loads the program stored in the hard disk 705, the programtransmitted from a satellite or a network, received by the communicationunit 708, and installed in the hard disk 705, or the program read fromthe removable recording media 711 mounted to a drive 709 and installedin the hard disk 705 to the RAM (Random Access Memory) 704 and executesthe program. Thereby, the CPU 702 executes the processing according tothe flowcharts described above or the processing executed by theconfigurations of the block diagrams described above. In addition, theCPU 702 outputs the processing result from the output unit 706configured using an LCD (Liquid Crystal Display) or a speaker, transmitsthe processing result from the communication unit 708, and records theprocessing result on the hard disk 705, through the input/outputinterface 710, according to necessity.

In the present specification, it is not necessary to process theprocessing steps describing the program for causing the computer toexecute the various processing in time series according to the orderdescribed as the flowcharts and processing executed in parallel orindividually (for example, parallel processing or processing using anobject) is also included.

The program may be processed by one computer or may be processed by aplurality of computers in a distributed manner. The program may betransmitted to a remote computer and may be executed.

An embodiment of the disclosure is not limited to the embodimentsdescribed above, and various changes and modifications may be madewithout departing from the scope of the disclosure.

That is, for example, (the parity check matrix initial value table of)the above-described new LDPC code can be used even if the communicationpath 13 (FIG. 7) is any of a satellite circuit, a ground wave, a cable(wire circuit) and others. In addition, the new LDPC code can also beused for data transmission other than digital broadcasting.

The GW patterns can be applied to a code other than the new LDPC code.Further, the modulation scheme to which the GW patterns are applied isnot limited to QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

The effects described in this specification are merely examples and notlimited, and any other effect may be obtained.

REFERENCE SIGNS LIST

-   11 transmitting device-   12 receiving device-   23 parity interleaver-   24 group-wise interleaver-   block interleaver-   54 block deinterleaver-   55 group-wise deinterleaver-   111 mode adaptation/multiplexer-   112 padder-   113 BB scrambler-   114 BCH encoder-   115 LDPC encoder-   116 bit interleaver-   117 mapper-   118 time interleaver-   119 SISO/MISO encoder-   120 frequency interleaver-   121 BCH encoder-   122 LDPC encoder-   123 mapper-   124 frequency interleaver-   131 frame builder/resource allocation unit-   132 OFDM generating unit-   151 OFDM operating unit-   152 frame managing unit-   153 frequency deinterleaver-   154 demapper-   155 LDPC decoder-   156 BCH decoder-   161 frequency deinterleaver-   162 SISO/MISO decoder-   163 time deinterleaver-   164 demapper-   165 bit deinterleaver-   166 LDPC decoder-   167 BCH decoder-   168 BB descrambler-   169 null deletion unit-   170 demultiplexer-   300 branch data storing memory-   301 selector-   302 check node calculating unit-   303 cyclic shift circuit-   304 branch data storing memory-   305 selector-   306 reception data memory-   307 variable node calculating unit-   308 cyclic shift circuit-   309 decoding word calculating unit-   310 reception data rearranging unit-   311 decoded data rearranging unit-   601 encoding processing unit-   602 storage unit-   611 encoding rate setting unit-   612 initial value table reading unit-   613 parity check matrix generating unit-   614 information bit reading unit-   615 encoding parity operation unit-   616 control unit-   701 bus-   702 CPU-   703 ROM-   704 RAM-   705 hard disk-   706 output unit-   707 input unit-   708 communication unit-   709 drive-   710 input/output interface-   711 removable recording media-   1001 reverse interchanging unit-   1002 memory-   1011 parity deinterleaver-   1101 acquiring unit-   1101 transmission path decoding processing unit-   1103 information source decoding processing unit-   1111 output unit-   1121 recording unit

The invention claimed is:
 1. A receiving device comprising: a receiverconfigured to receive a digital broadcast signal including a mappedgroup-wise interleaved low density parity check (LDPC) code word; andcircuitry configured to process the mapped group-wise interleaved LDPCcode word to obtain a group-wise interleaved LDPC code word, whereineach unit of two bits of the group-wise interleaved LDPC code word ismapped to one of 4 signal points of a first modulation scheme, or eachof a unit of four bits of the group-wise interleaved LDPC code word ismapped to one of 16 signal points of a second modulation scheme, or eachof a unit of six bits of the group-wise interleaved LDPC code word ismapped to one of 64 signal points of a third modulation scheme, processthe group-wise interleaved LDPC code word in units of bit groups of 360bits to obtain an LDPC code word of an LDPC code, wherein an (i+1)-thbit group from a head of the LDPC code word of the LDPC code isindicated by a bit group i, the LDPC code word of the LDPC code has asequence of bit groups 0 to 44, and the group-wise interleaved LDPC codeword has a following sequence of bit groups: 1, 4, 5, 6, 24, 21, 18, 7,17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22,13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and44, for the first modulation scheme, 27, 11, 20, 1, 7, 5, 29, 35, 9, 10,34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8,32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38, forthe second modulation scheme, or 14, 22, 18, 11, 28, 26, 2, 38, 10, 0,5, 12, 24, 17, 29, 16, 39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9,35, 40, 32, 30, 20, 36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4, for thethird modulation scheme, decode the LDPC code word of the LDPC code toobtain a decoded LDPC code work, and process the decoded LDPC code wordfor presentation of the digital broadcast signal, wherein the LDPC codehas a code length N of 16200 bits and a code rate r of 10/15 and the andis based on a parity check matrix initial value table listed as follows:352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 38214384 4470 4884 5012 5036 5084 5101 5271 5281 5353 505 915 1156 1269 15181650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 44394532 4940 5011 5076 5113 5367 268 346 650 919 1260 4389 4653 4721 48385054 5157 5162 5275 5362 220 236 828 1590 1792 3259 3647 4276 4281 43254963 4974 5003 5037 381 737 1099 1409 2364 2955 3228 3341 3473 3985 42574730 5173 5242 88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 45014901 5047 749 1502 2201 3189 2873 3245 3427 2158 2605 3165 1 3438 360610 3019 5221 371 2901 2923 9 3935 4683 1937 3502 3735 507 3128 4994 253854 4550 1178 4737 5366 2 223 5304 1146 5175 5197 1816 2313 3649 7401951 3844 1320 3703 4791 1754 2905 4058 7 917 5277 3048 3954 5396 48044824 5105 2812 3895 5226 0 5318 5358 1483 2324 4826 2266 4752
 5387.


2. A method for use by a receiving device the method comprising:receiving a digital broadcast signal including a mapped group-wiseinterleaved low density parity check (LDPC) code word; processing themapped group-wise interleaved LDPC code word to obtain a group-wiseinterleaved LDPC code word, wherein each unit of two bits of thegroup-wise interleaved LDPC code word is mapped to one of 4 signalpoints of a first modulation scheme, or each of a unit of four bits ofthe group-wise interleaved LDPC code word is mapped to one of 16 signalpoints of a second modulation scheme, or each of a unit of six bits ofthe group-wise interleaved LDPC code word is mapped to one of 64 signalpoints of a third modulation scheme; processing the group-wiseinterleaved LDPC code word in units of bit groups of 360 bits to obtainan LDPC code word of a LDPC code, wherein an (i+1)-th bit group from ahead of the LDPC code word of the LDPC code is indicated by a bit groupi, the LDPC code word of the LDPC code has a sequence of bit groups 0 to44, and the group-wise interleaved LDPC code word has a followingsequence of bit groups: 1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23,29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27,19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and 44, for the firstmodulation scheme, 27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28,6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12,2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38, for the secondmodulation scheme, or 14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5, 12, 24,17, 29, 16, 39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35, 40, 32,30, 20, 36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4, for the thirdmodulation scheme; decoding the LDPC code word of the LDPC code toobtain a decoded LDPC code word; and processing the decoded LDPC codeword for presentation of the digital broadcast signal, wherein the LDPCcode has a code length N of 16200 bits and a code rate r of 10/15 and isbased on a parity check matrix initial value table listed as follows:352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 38214384 4470 4884 5012 5036 5084 5101 5271 5281 5353 505 915 1156 1269 15181650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 44394532 4940 5011 5076 5113 5367 268 346 650 919 1260 4389 4653 4721 48385054 5157 5162 5275 5362 220 236 828 1590 1792 3259 3647 4276 4281 43254963 4974 5003 5037 381 737 1099 1409 2364 2955 3228 3341 3473 3985 42574730 5173 5242 88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 45014901 5047 749 1502 2201 3189 2873 3245 3427 2158 2605 3165 1 3438 360610 3019 5221 371 2901 2923 9 3935 4683 1937 3502 3735 507 3128 4994 253854 4550 1178 4737 5366 2 223 5304 1146 5175 5197 1816 2313 3649 7401951 3844 1320 3703 4791 1754 2905 4058 7 917 5277 3048 3954 5396 48044824 5105 2812 3895 5226 0 5318 5358 1483 2324 4826 2266 4752
 5387.


3. A transmitting device comprising: circuitry configured to receivedata to be transmitted in a digital broadcast signal, perform lowdensity parity check (LDPC) encoding on input bits of the received datato obtain an encoded LDPC code word of an LDPC code, wherein the LDPCcode has a code length N of 16200 bits and a code rate r of 10/15 and isbased on a parity check matrix initial value table listed as follows:352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 38214384 4470 4884 5012 5036 5084 5101 5271 5281 5353 505 915 1156 1269 15181650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 44394532 4940 5011 5076 5113 5367 268 346 650 919 1260 4389 4653 4721 48385054 5157 5162 5275 5362 220 236 828 1590 1792 3259 3647 4276 4281 43254963 4974 5003 5037 381 737 1099 1409 2364 2955 3228 3341 3473 3985 42574730 5173 5242 88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 45014901 5047 749 1502 2201 3189 2873 3245 3427 2158 2605 3165 1 3438 360610 3019 5221 371 2901 2923 9 3935 4683 1937 3502 3735 507 3128 4994 253854 4550 1178 4737 5366 2 223 5304 1146 5175 5197 1816 2313 3649 7401951 3844 1320 3703 4791 1754 2905 4058 7 917 5277 3048 3954 5396 48044824 5105 2812 3895 5226 0 5318 5358 1483 2324 4826 2266 4752 5387,

group-wise interleave the LDPC code word in units of bit groups of 360bits to generate a group-wise interleaved LDPC code word wherein an(i+1)-th bit group from a head of the LDPC code word of the LDPC code isindicated by a bit group i, the LDPC code word of the LDPC code has asequence of bit groups 0 to 44, and the group-wise interleaved LDPC codeword has a following sequence of bit groups: 1, 4, 5, 6, 24, 21, 18, 7,17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22,13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and44, for a first modulation scheme, 27, 11, 20, 1, 7, 5, 29, 35, 9, 10,34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8,32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38 forasecond modulation scheme, or 14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5,12, 24, 17, 29, 16, 39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35,40, 32, 30, 20, 36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4, for a thirdmodulation scheme, map the group-wise interleaved LDPC code word inunits of two bits to any one of 4 signal points in the first modulationscheme, or in units of four bits to any one of 16 signal points in thesecond modulation scheme, or in units of six bits to any one of 64signal points in the third modulation scheme, and; transmit the digitalbroadcast signal including the mapped group-wise interleaved LDPC codeword.
 4. A method for generating a digital broadcast signal, comprising:receiving data to be transmitted in a digital broadcast signal;performing low density parity check (LDPC) encoding on input bits of thereceived data to obtain an encoded LDPC code word of an LDPC code,wherein the LDPC code has a code length N of 16200 bits and a code rater of 10/15 and is based on a parity check matrix initial value tablelisted as follows: 352 747 894 1437 1688 1807 1883 2119 2159 3321 34003543 3588 3770 3821 4384 4470 4884 5012 5036 5084 5101 5271 5281 5353505 915 1156 1269 1518 1650 2153 2256 2344 2465 2509 2867 2875 3007 32543519 3687 4331 4439 4532 4940 5011 5076 5113 5367 268 346 650 919 12604389 4653 4721 4838 5054 5157 5162 5275 5362 220 236 828 1590 1792 32593647 4276 4281 4325 4963 4974 5003 5037 381 737 1099 1409 2364 2955 32283341 3473 3985 4257 4730 5173 5242 88 771 1640 1737 1803 2408 2575 29743167 3464 3780 4501 4901 5047 749 1502 2201 3189 2873 3245 3427 21582605 3165 1 3438 3606 10 3019 5221 371 2901 2923 9 3935 4683 1937 35023735 507 3128 4994 25 3854 4550 1178 4737 5366 2 223 5304 1146 5175 51971816 2313 3649 740 1951 3844 1320 3703 4791 1754 2905 4058 7 917 52773048 3954 5396 4804 4824 5105 2812 3895 5226 0 5318 5358 1483 2324 48262266 4752 5387;

group-wise interleaving the LDPC code word in units of bit groups of 360bits to generate a group-wise interleaved LDPC code word, wherein an(i+1)-th bit group from a head of the LDPC code word of the LDPC code isindicated by a bit group i, the LDPC code word of the LDPC code has asequence of bit groups 0 to 44, and the group-wise interleaved LDPC codeword has a following sequence of bit groups: 1, 4, 5, 6, 24, 21, 18, 7,17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22,13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and44, fora first modulation scheme, 27, 11, 20, 1, 7, 5, 29, 35, 9, 10,34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8,32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38, for asecond modulation scheme, or 14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5,12, 24, 17, 29, 16, 39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35,40, 32, 30, 20, 36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4, fora thirdmodulation scheme; mapping the group-wise interleaved LDPC code word inunits of two bits to any one of 4 signal points in the first modulationscheme, or in units of four bits to any one of 16 signal points in thesecond modulation scheme, or in units of six bits to any one of 64signal points in the third modulation scheme; and transmitting thedigital broadcast signal including the mapped group-wise interleavedLDPC code word.